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A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The

A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.

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1. A two-stage gate driver circuit for driving a junction field effect transistor having a gate, a source, and a drain, the two-stage gate driver circuit comprising: an input for receiving an input control pulse signal with which switching of the junction field effect transistor is to be synchronize

1. A two-stage gate driver circuit for driving a junction field effect transistor having a gate, a source, and a drain, the two-stage gate driver circuit comprising: an input for receiving an input control pulse signal with which switching of the junction field effect transistor is to be synchronized;a first on circuit that provides, in response to the input control pulse signal, a forward gate current to the junction field effect transistor at least during a conduction stage of the junction field effect transistor;a second turn-on circuit that provides, in response to the input control pulse signal, a current to charge the gate during at least part of a turn-on stage of the junction field effect transistor, wherein the current to charge the gate is relatively higher than the forward gate current; anda pull-down circuit,wherein the first on circuit, the second turn-on circuit and the pull-down circuit are electrically coupled between the input and the gate of the junction field effect transistor in parallel, andwherein the current to charge the gate during at least part of a turn-on stage of the junction field effect transistor is a pulse that terminates while the forward gate current is provided by the first on circuit. 2. The two-stage gate driver circuit of claim 1, wherein the first on circuit comprises: a first switch having a gate, a source electrically coupled to the gate of the junction field effect transistor through a first resistor and a drain electrically coupled to a first current source for providing a first positive voltage; anda pulse generator electrically coupled between the input and the gate of the first switch. 3. The two-stage gate driver circuit of claim 2, wherein the pulse generator is configured such that the pulse generator responds to supply of the input control pulse signal by generating a corresponding control pulse signal that is in synchronization with the input control pulse signal. 4. The two-stage gate driver circuit of claim 3, wherein the generated control pulse signal has a first pulse duration that is equal to or less than 15% of the pulse on duration of the input control pulse signal. 5. The two-stage gate driver circuit of claim 3, wherein the generated control pulse signal has a first pulse duration that is adjustable manually. 6. A two-stage gate driver circuit for driving a junction field effect transistor having a gate, a source, and a drain, the two-stage gate driver circuit comprising: an input for receiving an input control pulse signal with which switching of the junction field effect transistor is to be synchronized;a first on circuit that provides, in response to the input control pulse signal, a forward gate current to the junction field effect transistor at least during a conduction stage of the junction field effect transistor, wherein the first on circuit comprisesa first switch having a gate, a source electrically coupled to the gate of the junction field effect transistor through a first resistor and a drain electrically coupled to a first current source for providing a first positive voltage, anda pulse generator electrically coupled between the input and the gate of the first switch, wherein the pulse generator is configured such that the pulse generator responds to supply of the input control pulse signal by generating a corresponding control pulse signal that is in synchronization with the input control pulse signal, wherein the generated control pulse signal has a first pulse duration of the generated control pulse signal that is adjustable automatically in accordance with a feedback signal from the junction field effect transistor;a second turn-on circuit that provides, in response to the input control pulse signal, a current to charge the gate during at least part of a turn-on stage of the junction field effect transistor, wherein the current to charge the gate is relatively higher than the forward gate current; anda pull-down circuit,wherein the first on circuit, the second turn-on circuit and the pull-down circuit are electrically coupled between the input and the gate of the junction field effect transistor in parallel. 7. The two-stage gate driver circuit of claim 1, wherein the second turn-on circuit comprises a second switch having a gate electrically coupled to the input,a source electrically coupled to the gate of the junction field effect transistor through a second resistor, anda drain electrically coupled to a second current source for providing a second positive voltage. 8. The two-stage gate driver circuit of claim 7, wherein the pull-down circuit comprises: a third switch having a gate;a source electrically coupled to a third current source for providing a negative voltage;a drain electrically coupled to the gate of the junction field effect transistor through a third resistor; andan inverter electrically coupled between the input and the gate of the third switch. 9. The two-stage gate driver circuit of claim 1, wherein the first on circuit is electrically coupled between a first current source and the gate of the junction field effect transistor through a first resistor, wherein the first current source is adapted for providing a first positive voltage. 10. The two-stage gate driver circuit of claim 9, wherein: the first on circuit is turned on for a first duration that is equal to or less than 15% of the pulse on duration of the control pulse signal in response to the input control pulse signal; andthe first on circuit is turned off for the pulse-off duration in response to the input control pulse signal. 11. The two-stage gate driver circuit of claim 10, wherein the second on circuit is electrically coupled between a second current source and the gate of the junction field effect transistor through a second resistor, wherein resistance of the first resistor>resistance of the second resistor, and wherein the second current source is adapted for providing a second positive voltage. 12. The two-stage gate driver circuit of claim 11, wherein the first and second current sources correspond to a single current source or to two different current sources. 13. The two-stage gate driver circuit of claim 11, wherein the pull-down circuit is electrically coupled between a third current source and the gate of the junction field effect transistor through a third resistor, wherein the third current source is adapted for providing a negative voltage. 14. The two-stage gate driver circuit of claim 1, wherein the junction field effect transistor is a wide bandgap junction field effect transistor or a SiC junction field effect transistor. 15. The two-stage gate driver circuit of claim 1, wherein the forward gate current and the current to charge the gate begin essentially simultaneously. 16. The two-stage gate driver circuit of claim 1, wherein the first on circuit and the second turn-on circuit are of a single integrated circuit. 17. The two-stage gate driver circuit of claim 1, wherein the current to charge the gate during at least part of a turn-on stage of the junction field effect transistor causes the gate voltage to overshoot. 18. The two-stage gate driver circuit of claim 1, wherein the pulse lasts at least until a turn-on time of the junction field effect transistor. 19. The two-stage gate driver circuit of claim 18, wherein the pulse exceeds the turn-on time by less than 100 ns. 20. The two-stage gate driver circuit of claim 12, wherein the first on circuit comprises a current-limiting resistor having a resistance sized to set the forward gate current while stepping down a voltage to a voltage required by the gate of the junction field effect transistor. 21. The two-stage gate driver circuit of claim 1, wherein the pull-down circuit uses a complement of the input control pulse signal in pulling the gate of the junction field effect transistor low.