Computer or microchip including a network portion with RAM memory erasable by a firewall-protected master controller
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-015/16
G06F-011/00
H04L-029/08
A01N-025/30
G06F-001/16
G06F-009/50
G06F-011/16
G06F-011/20
G06F-015/76
G06F-021/00
H04L-012/26
H04L-029/06
출원번호
US-0092707
(2013-11-27)
등록번호
US-9021011
(2015-04-28)
발명자
/ 주소
Ellis, Frampton E.
출원인 / 주소
Ellis, Frampton E.
대리인 / 주소
Mendelsohn, Drucker & Dunleavy, P.C.
인용정보
피인용 횟수 :
0인용 특허 :
181
초록▼
A computer or microchip including a master controlling device, network communication components, one or more microprocessors and RAM, an internal hardware firewall located between a protected portion that is protected by the internal hardware firewall and a network portion. The internal hardware fir
A computer or microchip including a master controlling device, network communication components, one or more microprocessors and RAM, an internal hardware firewall located between a protected portion that is protected by the internal hardware firewall and a network portion. The internal hardware firewall denies access to at least the protected portion of the computer or microchip from the network. The firewall permits unrestricted access by the network to the network portion so that processing operations other than network communications and firewall operations conducted with the network are executed by microprocessors and RAM in the network portion. The master controlling device has preemptive control of the microprocessors and RAM in the network portion including erasure of at least a part of the random access memory (RAM) prior to the use of the network portion of the computer or microchip by the user or the operating system.
대표청구항▼
1. A computer or microchip, comprising: a master controlling device of the computer or microchip, an internal hardware firewall having a location between a protected portion of the computer or microchip that is protected by the internal hardware firewall and a network portion of the computer or micr
1. A computer or microchip, comprising: a master controlling device of the computer or microchip, an internal hardware firewall having a location between a protected portion of the computer or microchip that is protected by the internal hardware firewall and a network portion of the computer or microchip, the network portion having a connection for a network of computers including the World Wide Web and/or the Internet; the internal hardware firewall denies access to at least the protected portion of the computer or microchip from the network; and network communications devices located in the network portion of the computer or microchip; andone or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors or processing units and random access memory (RAM) that are not network communications devices, wherein the one or more microprocessors or processing units and random access memory (RAM) are located in the network portion of the computer or microchip and are separate from the internal hardware firewall; andwherein the location of the internal hardware firewall permits unrestricted access by the network of computers to the network portion of the computer or microchip so that processing operations other than network communications and firewall operations conducted by the computer or microchip with the network of computers are executed by one or more of the microprocessors or processing units and random access memory (RAM) in the network portion of the computer or microchip: andwherein the master controlling device is located in the protected portion of the computer or microchip and has preemptive control of the microprocessors or processing units and random access memory (RAM) in the network portion of the computer or microchip, andthe preemptive control including erasure of at least a part of the random access memory (RAM) in the network portion of the computer or microchip prior to use of the network portion of the computer or microchip by a user or operating system of the computer or microchip. 2. The computer or microchip of claim 1, wherein the preemptive control includes erasure of all of the random access memory (RAM) in the network portion of the computer or microchip prior to the use of the network portion of the computer or microchip by the user or the operating system of the computer or microchip. 3. The computer or microchip of claim 1, wherein all or part of the random access memory (RAM) in the network portion is erased prior to network use of the network portion of the computer or microchip. 4. The computer or microchip of claim 1, wherein the erasure of the part of the random access memory (RAM) in the network portion is by the user or by the operating system. 5. The computer or microchip of claim 2, wherein the erasure of all of the random access memory (RAM) in the network portion is by the user or by the operating system. 6. The computer or microchip of claim 2, wherein all or part of the random access memory (RAM) in the network portion is volatile memory and is erased by power interruption to the random access memory (RAM). 7. The computer or microchip of claim 2, wherein all or part of the random access memory (RAM) in the network portion is non-volatile memory and is erased by overwriting the random access memory (RAM). 8. The computer or microchip of claim 2, wherein the computer or microchip includes one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 additional internal firewalls, each protecting a microprocessor or processing unit with an integrated random access memory (RAM). 9. The computer or microchip of claim 2, wherein the protected portion of the computer or microchip includes random access memory (RAM) protected by one or more additional internal firewalls. 10. The computer or microchip of claim 2, wherein the protected portion and/or the network portion of the computer or microchip include one or more additional internal firewalls. 11. The computer or microchip of claim 8, wherein the computer or microchip is configured so that the user or the operating system of the computer or microchip saves one or more files in at least a part of the random access memory (RAM). 12. The computer or microchip of claim 10, wherein the computer or microchip is configured so that the user or the operating system of the computer or microchip uses the network portion of the computer or microchip and saves one or more files in random access memory (RAM) that is located in the network portion of the computer or microchip and that is protected by the one or more additional internal firewalls. 13. The computer or microchip of claim 10, wherein the computer or microchip is configured so that the user or the operating system of the computer or microchip uses the network portion of the computer or microchip and transfers one or more files between the network portion and random access memory (RAM) that is located in the protected portion of the computer or microchip and that is protected by one or additional internal firewalls. 14. A computer or microchip comprising: a master controlling device of the computer or microchip, an internal hardware firewall located between a protected portion of the computer or microchip that is protected by the internal hardware firewall and a network portion of the computer or microchip, the network portion having a connection for a network of computers including the World Wide Web and/or the Internet; the internal hardware firewall denies access to at least the protected portion of the computer or microchip from the network; and network communications devices located in the network portion of the computer or microchip; andone or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors or processing units and random access memory (RAM) that are not network communications devices, wherein the one or more microprocessors or processing units and random access memory (RAM) are located in the network portion of the computer or microchip and are separate from the internal hardware firewall; andwherein a location of the internal hardware firewall permits unrestricted access by the network of computers to the network portion of the computer or microchip so that processing operations other than network communications and firewall operations conducted by the computer or microchip with the network of computers are executed by one or more of the microprocessors or processing units and random access memory (RAM) in the network portion of the computer or microchip; andwherein the master controlling device is located in the protected portion of the computer or microchip and has preemptive control of the microprocessors or processing units and random access memory (RAM) in the network portion of the computer or microchip, andthe preemptive control including erasure of at least a part of the random access memory (RAM) in the network portion of the computer or microchip prior to use of the network portion of the computer or microchip by a user or operating system of the computer or microchip, and wherein at least a portion of the computer or microchip is surrounded by a first Faraday Cage. 15. The computer or microchip of claim 14, wherein the computer or microchip is surrounded by a second Faraday Cage. 16. The computer or microchip of claim 15, wherein the computer or microchip is surrounded by a second Faraday Cage. 17. A computer or microchip comprising: a master controlling device of the computer or microchip, an internal hardware firewall located between a protected portion of the computer or microchip that is protected by the internal hardware firewall and a network portion of the computer or microchip, the network portion having a connection for a network of computers including the World Wide Web and/or the Internet; the internal hardware firewall denies access to at least the protected portion of the computer or microchip from the network; and network communications devices located in the network portion of the computer or microchip; andone or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors or processing units and random access memory (RAM) that are not network communications devices, wherein the one or more microprocessors or processing units and random access memory (RAM) are located in the network portion of the computer or microchip and are separate from the internal hardware firewall; andwherein a location of the internal hardware firewall permits unrestricted access by the network of computers to the network portion of the computer or microchip so that processing operations other than network communications and firewall operations conducted by the computer or microchip with the network of computers are executed by one or more of the microprocessors or processing units and random access memory (RAM) in the network portion of the computer or microchip; andwherein the master controlling device is located in the protected portion of the computer or microchip and has preemptive control of the microprocessors or processing units and random access memory (RAM) in the network portion of the computer or microchip, andthe preemptive control including erasure of at least a part of the random access memory (RA M) in the network portion of the computer or microchip prior to use of the network portion of the computer or microchip by a user or operating system of the computer or microchip, and wherein the erasure of the part of the random access memory (RAM) in the network portion is by the user or by the operating system and the computer or microchip is a personal computer or microchip and the user is a personal user. 18. The computer or microchip of claim 17, wherein the computer or microchip is surrounded by a first Faraday Cage. 19. The computer or microchip of claim 11, wherein the computer or microchip is a personal computer or microchip and the user is a personal user. 20. The computer or microchip of claim 12, wherein the computer or microchip is a personal computer or microchip and the user is a personal user. 21. The computer or microchip of claim 13, wherein the computer or microchip is a personal computer or microchip and the user is a personal user.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (181)
Nielsen Keith E. (Redondo Beach CA), Active energy control for diode pumped laser systems using pulsewidth modulation.
Benkeser Donald E. (Naperville IL) Cyr Joseph B. (Aurora IL) Greenberg Albert G. (Millburn NJ) Wright Paul E. (Basking Ridge NJ), Adaptive job scheduling for multiprocessing systems with master and slave processors executing tasks with opposite antic.
Bonneau ; Jr. Walt C. (Missouri City TX) Guttag Karl (Missouri City TX) Gove Robert (Dallas TX), Architecture of a chip having multiple processors and multiple memories.
Russell David S. (Minneapolis MN) Fischer Larry G. (Waseca MN) Wala Philip M. (Waseca MN) Ratliff Charles R. (Crystal Lake IL) Brennan Jeffrey (Waseca MN), Cellular communications system with centralized base stations and distributed antenna units.
Naedel Richard G. (Rockville MD) Harris David B. (Columbia MD) Uehling Mark (Bowie MD), Chassis and personal computer for severe environment embedded applications.
Berkowitz David B. (Palo Alto CA) Hao Ming C. (Los Altos CA) Lieu Hung C. (Santa Clara CA) Snow Franklin D. (Saratoga CA), Collaborative computing system using pseudo server process to allow input from different server processes individually a.
Sumimoto Shinji (Kawasaki JPX), Computer resource distributing method and system for distributing a multiplicity of processes to a plurality of computer.
Passera Anthony ; Thorp John R. ; Beckerle Michael J. ; Zyszkowski Edward S. A., Computer system and computerized method for partitioning data for parallel processing.
Jones Oliver (Andover MA) Deshon Mary (Winthrop MA) Ericsson Staffan (Brookline MA) Flach James (Cave Creek AZ), Computer teleconferencing method and apparatus.
Ellis, III, Frampton E., Computers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartments.
Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall and an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary inner hardware firewalls.
Glick James A. (Granite Shoals TX) Graczyk Ronald B. (Round Rock TX) Nurick Albert F. (Austin TX) Fraley Brittain D. (Austin TX), Computing and multimedia entertainment system.
Leung Wing Y. (Cupertino CA) Hsu Fu-Chieh (Saratoga CA), Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale in.
Morley Richard E. (Greenville NH), Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and met.
Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Riegelhaupt Norbert H. (Framingham MA), Dual-rail processor with error checking at single rail interfaces.
Rosenberry Steven (Reading PA), Dynamic fault-tolerant parallel processing system for performing an application function with increased efficiency using.
Pian Chao-Kuang (Anaheim CA) Habereder Hans L. (Orange CA), Dynamic task allocation in a multi-processor system employing distributed control processors and distributed arithmetic.
Pezeshki Bardia (Huntington Beach CA) Harris ; Jr. James S. (Stanford CA), Electrostatically tunable optical device and optical interconnect for processors.
Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Fully scalable parallel processing system having asynchronous SIMD processing.
Nguyen Tam M. (Valhalla NY) Rana Deepak (Yorktown Heights NY) Ruiz Antonio (Yorktown Heights NY) Willner Barry E. (Briarcliff Manor NY), Hybrid digital/analog multimedia hub with dynamically allocated/released channels for video processing and distribution.
Fucito Michele (Meta ITX) Recchia Maruo (Rome ITX) Puglia Silvestro (Pomezia ITX) Mariani Claudio (Rome ITX) Colangeli Giulio (Gerenzano di Roma ITX) Rotunno Antonio (Salerno ITX), Interface unit for dynamically configuring a buffer in different modes to store data transfers based upon different conn.
Guy Charles B. (Hillsboro OR) Cadambi Sudarshan B. (Beaverton OR) Gutmann Michael J. (Portland OR) Bhasker Narjala (Portland OR) Trethewey Jim R. (Beaverton OR) McArdle Brian J. (Beaverton OR), Interrupt distribution scheme for a computer bus.
Wade Jon P. ; Cassiday Daniel R. ; Lordi Robert D. ; Steele ; Jr. Guy Lewis ; St. Pierre Margaret A. ; Wong-Chan Monica C. ; Abuhamdeh Zahi S. ; Douglas David C. ; Ganmukhi Mahesh N. ; Hill Jeffrey V, Massively parallel computer including auxiliary vector processor.
Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L., Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network an.
Bruckert William (Northboro MA) Kovalcin David (Grafton MA) Bissett Thomas D. (Derry NH) Munzer John (Brookline MA) Mazur Dennis (Worcester MA) Mott ; Jr. Peter R. (Worcester MA) Dearth Glenn A. (Hud, Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having.
Ault Donald Fred ; Bender Ernest Scott ; Spiegel Michael Gary, Method and apparatus for creating a security environment for a user task in a client/server system.
Kisor Greg, Method and system including a central computer that assigns tasks to idle workstations using availability schedules and computational capabilities.
Farnworth Warren M. (Boise ID) Duesman Kevin (Boise ID) Heitzeberg Ed (Boise ID), Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers.
Rausch Dieter (Karlsruhe DEX), Method for preventing an overload when starting a multicomputer system and multicomputer system for carrying out said me.
Shorter David U. (Lewisville TX), Method for scheduling execution of distributed application programs at preset times in an SNA LU 6.2 network environment.
Harris Jonathan P. (Littleton MA) Leibholz Daniel (Watertown MA) Miller Brad (Westborough MA), Method of dynamically allocating processors in a massively parallel processing system.
Ellis, Frampton E., Method of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Ellis, Frampton E., Methods of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Hu Ming K. (Syracuse NY) Jia Yau G. (Nanjing ; Jiangsu CNX), Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors.
Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce, N-dimensional modified hypercube.
Hodge Winston W. (Yorba Linda CA) Taylor Lawrence E. (Anaheim CA), Near-video-on-demand digital video distribution system utilizing asymmetric digital subscriber lines.
Georgiou,Christos J.; Gregurick,Victor L.; Nair,Indira; Salapura,Valentina, Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus.
Hinsley Christopher Andrew,GBX, Operating system for use with computer networks incorporating one or more data processors linked together for parallel p.
Chin Danny (Robbinsville NJ) Sauer Donald J. (Allentown NJ) Meyerhofer Dietrich (Princeton NJ) Katsuki Kazuo (Hyogo JPX), Parallel digital processing system using optical interconnection between control sections and data processing sections.
Beatty Harry J. (Clinton Corners NY) Elmendorf Peter C. (Kingston NY) Gillis Roland R. (Ulster Park NY) Pramanick Ira (Wappingers Falls NY), Parallel execution of a complex task partitioned into a plurality of entities.
Beatty Harry John ; Elmendorf Peter Claude ; Gillis Roland Roberto ; Pramanick Ira, Parallel execution of a complex task partitioned into a plurality of entities.
Bahr James E. (Rochester MN) Corrigan Michael J. (Rochester MN) Knipfer Diane L. (Rochester MN) McMahon Lynn A. (Rochester MN) Metzger Charlotte B. (Elgin MN), Process for dispatching tasks among multiple information processors.
Nelson Darul J. ; Noval James V. ; Suarez Ricardo E. ; Aghazadeh Mostafa A., Processor card assembly including a heat sink attachment plate and an EMI/ESD shielding cage.
Gregerson Daniel P. ; Farrell David R. ; Gaitonde Sunil S. ; Ahuja Ratinder P. ; Ramakrishnan Krish ; Shafiq Muhammad ; Wallis Ian F., Scalable distributed computing environment.
Ohta Hiroyuki,JPX ; Miura Hideo,JPX ; Usami Mitsuo,JPX ; Kametani Masatsugu,JPX ; Zen Munetoshi,JPX ; Okamoto Noriaki,JPX, Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same.
Danahy John J. ; Kinney Daryl F. ; Pulsinelli Gary S. ; Rose Lawrence J. ; Kumar Navaneet, Service-centric monitoring system and method for monitoring of distributed services in a computing network.
Hoover Russell D. (Rochester MN) Willis John C. (Rochester MN) Baldus Donald F. (Mazeppa MN) Ziegler Frederick J. (Rochester MN) Liu Lishing (Pleasantville NY), System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data p.
Teper Jeffrey A. ; Koneru Sudheer ; Mangione Gordon ; Balaz Rudolph ; Contorer Aaron M. ; Chao Lucy, System and method for providing trusted brokering services over a distributed network.
Chasek Norman E. (24 Briar Brae Rd. Stamford CT 06903), System for developing real time economic incentives to encourage efficient use of the resources of a regulated electric.
Leclercq Thierry (Paris FRX) Sallio Patrick (Thorigne-Fouillard FRX), System for management of the usage of data consultations in a telecommunication network.
Choquier Philippe,FRX ; Peyroux Jean-Francios ; Griffin William J., System for on-line service in which gateway computer uses service map which includes loading condition of servers broad.
Baehr Geoffrey G. ; Danielson William ; Lyon Thomas L. ; Mulligan Geoffrey ; Patterson Martin,FRX ; Scott Glenn C. ; Turbyfill Carolyn, System for packet filtering of data packets at a computer network interface.
Shwed Gil,ILX ; Kramer Shlomo,ILX ; Zuk Nir,ILX ; Dogon Gil,ILX ; Ben-Reuven Ehud,ILX, System for securing the flow of and selectively modifying packets in a computer network.
Padgaonkar Ajay J. (Phoenix AZ) Mitra Sumit K. (Tempe AZ), System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory.
Kraft Reiner ; Lu Qi ; Wisebond Marat, Task distribution processing system and the method for subscribing computers to perform computing tasks during idle time.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.