Method and structure of monolithically integrated IC and resistive memory using IC foundry-compatible processes
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G11C-011/00
H01L-027/24
G11C-013/00
H01L-045/00
출원번호
US-0072657
(2013-11-05)
등록번호
US-9036400
(2015-05-19)
발명자
/ 주소
Lu, Wei
출원인 / 주소
Crossbar, Inc.
대리인 / 주소
Ogawa P.C.
인용정보
피인용 횟수 :
2인용 특허 :
124
초록▼
The present invention relates to integrating a resistive memory device on top of an IC substrate monolithically using IC-foundry compatible processes. A method for forming an integrated circuit includes receiving a semiconductor substrate having a CMOS IC device formed on a surface region, forming a
The present invention relates to integrating a resistive memory device on top of an IC substrate monolithically using IC-foundry compatible processes. A method for forming an integrated circuit includes receiving a semiconductor substrate having a CMOS IC device formed on a surface region, forming a dielectric layer overlying the CMOS IC device, forming first electrodes over the dielectric layer in a first direction, forming second electrodes over the first electrodes in along a second direction different from the first direction, and forming a two-terminal resistive memory cell at each intersection of the first electrodes and the second electrodes using foundry-compatible processes, including: forming a resistive switching material having a controllable resistance, disposing an interface material including p-doped polycrystalline silicon germanium—containing material between the resistive switching material and the first electrodes, and disposing an active metal material between the resistive switching material and the second electrodes.
대표청구항▼
1. A monolithic integrated circuit and crossbar array comprising: a semiconductor substrate having a first surface region;one or more CMOS integrated circuit devices provided on the surface region of the semiconductor substrate;a dielectric layer overlying the one or more CMOS integrated circuit dev
1. A monolithic integrated circuit and crossbar array comprising: a semiconductor substrate having a first surface region;one or more CMOS integrated circuit devices provided on the surface region of the semiconductor substrate;a dielectric layer overlying the one or more CMOS integrated circuit devices;a first plurality of electrodes overlying the dielectric layer and extending along a first direction;a second plurality of electrodes overlying the first plurality of electrodes and extending along a second direction, wherein the first direction and the second direction are different; andwherein intersections of the first plurality of electrodes and the second plurality of electrodes define a two-terminal resistive memory cell comprising: a resistive switching material having a controllable resistance;an interface material disposed between the resistive switching material and the first plurality of electrodes, wherein the interface material comprises a foundry-compatible p-doped polycrystalline silicon germanium—containing material; andan active metal material disposed between the resistive switching material and the second plurality of electrodes. 2. The monolithic integrated circuit and crossbar array of claim 1, wherein the resistive switching material comprises amorphous silicon. 3. The monolithic integrated circuit and crossbar array of claim 2, wherein the resistive switching material comprises a nano-pillar structure disposed between first plurality of electrodes and the second plurality of electrodes;wherein the active metal material is selected from a group consisting of: silver (Ag), gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V) and cobalt (Co). 4. The monolithic integrated circuit and crossbar array of claim 1, wherein the polycrystalline silicon-germanium material has a concentration within a range of about 60% Ge to about 80% g Ge. 5. The monolithic integrated circuit and crossbar array of claim 1, wherein the polycrystalline silicon-germanium-containing material has a concentration within a range of about 70% Ge to about 80% Ge; andwherein the polycrystalline silicon-germanium-containing material is formed by using a deposition temperature within a range of about 380° C. to about 420° C. 6. The monolithic integrated circuit and crossbar array of claim 1, wherein the polycrystalline silicon-germanium-containing material is deposited at a temperature of about 400° C. 7. The monolithic integrated circuit and crossbar array of claim 1, wherein the polycrystalline silicon-germanium-material is doped with boron with a doping concentration within a range of about 10E17/cm3 to about 10E20/cm3. 8. The monolithic integrated circuit and crossbar array of claim 1, wherein the resistive switching material is configured to have a ratio of an on resistance to off resistance within a range of about 10E3 to about 10E7. 9. The monolithic integrated circuit and crossbar array of claim 1, wherein the one or more CMOS integrated circuit devices provided on the surface region of the semiconductor substrate comprises a MOS transistor. 10. The monolithic integrated circuit and crossbar array of claim 1 further comprising a plurality of electrical contacts between the one or more CMOS integrated circuit devices and the first plurality of electrodes. 11. A method for forming an integrated circuit comprising: receiving a semiconductor substrate having one or more CMOS integrated circuit devices formed on a surface region of the semiconductor substrate;forming a dielectric layer overlying the one or more CMOS integrated circuit devices;forming a first plurality of electrodes overlying the dielectric layer and extending along a first direction;forming a second plurality of electrodes overlying the first plurality of electrodes and extending along a second direction, wherein the first direction and the second direction are different; andforming a two-terminal resistive memory cell at intersections of the first plurality of electrodes and the second plurality of electrodes using foundry-compatible processes, comprising: forming a resistive switching material having a controllable resistance;disposing an interface material between the resistive switching material and the first plurality of electrodes, wherein the interface material comprises p-doped polycrystalline silicon germanium—containing material; anddisposing an active metal material between the resistive switching material and the second plurality of electrodes. 12. The method of claim 11, wherein the forming the resistive switching material comprises depositing amorphous silicon material. 13. The method of claim 12, wherein the forming the resistive switching material further comprises: forming a nano-pillar structure between the first plurality of electrodes and the second plurality of electrodes;wherein the active metal material is selected from a group consisting of: silver (Ag), gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V) and cobalt (Co). 14. The method of claim 11, wherein the polycrystalline silicon-germanium material has a concentration within a range of about 60% Ge to about 80% g GE. 15. The method of claim 12 wherein forming the polycrystalline silicon-germanium-containing material comprises depositing the polycrystalline silicon germanium-containing material at a deposition temperature within a range of about 380° C. to about 420° C. 16. The method of claim 11 wherein the disposing the interface material comprises doping the polycrystalline silicon germanium-containing material with boron with a doping concentration within a range of about 10E17/cm3 to about 10E20/cm3. 17. The method of claim 11, wherein the resistive switching material comprises an electric field controllable resistance via metal ion migration. 18. The method of claim 11 wherein the receiving the semiconductor substrate comprises: receiving the semiconductor substrate having the surface region; andforming the one or more CMOS integrated circuit devices on the surface region using foundry-compatible processes. 19. The method of claim 18 wherein the forming the one or more CMOS integrated circuit devices comprises forming a MOS transistor on the surface region. 20. The method claim 11 further comprising forming a plurality of electrical contacts between the one or more CMOS integrated circuit devices and the first plurality of electrodes.
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