Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-015/17
G06F-015/177
G06F-015/78
출원번호
US-0082691
(2013-11-18)
등록번호
US-9037834
(2015-05-19)
발명자
/ 주소
Plunkett, Robert T.
Heidari, Ghobad
Master, Paul L.
출원인 / 주소
Altera Corporation
대리인 / 주소
Nixon Peabody LLP
인용정보
피인용 횟수 :
0인용 특허 :
430
초록▼
An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information.
An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.
대표청구항▼
1. An adaptive computing integrated circuit configurable to perform a plurality of functions, the integrated circuit comprising: a plurality of heterogeneous computational elements; andan interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection ne
1. An adaptive computing integrated circuit configurable to perform a plurality of functions, the integrated circuit comprising: a plurality of heterogeneous computational elements; andan interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network changing interconnections between the plurality of heterogeneous computational elements in response to configuration information;wherein a first group of computational elements of the plurality of heterogeneous computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements;wherein a second group of computational elements of the plurality of heterogeneous computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements; andwherein one or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements. 2. The adaptive computing integrated circuit of claim 1, wherein the one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form one or more additional instances of the first version of the functional unit. 3. The adaptive computing integrated circuit of claim 1, wherein one or more of the first group of heterogeneous computational elements or one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form a third version of a functional unit to perform the first function. 4. The adaptive computing integrated circuit of claim 1 wherein if the second function is not currently used, one or more of the first or second group of heterogeneous computational elements are reconfigurable by the interconnection network to implement a third function. 5. The adaptive computing integrated circuit of claim 1, wherein a third group of computational elements are reconfigured for a third function, wherein the third group of computational elements are used for one of functional units to perform the first function if the third function is not used. 6. The adaptive integrated circuit of claim 1, wherein the first group of computational elements is reconfigured to the second version of the functional unit to perform the first function based on parameters including energy use, speed of performing the first function, or hardware availability. 7. The adaptive integrated circuit of claim 1, wherein the first and second functions are part of a sequential operation and wherein the one or more of the second group of heterogeneous computational elements is reconfigured to perform the second function after the first function is performed. 8. An adaptive computing integrated circuit configurable to perform a plurality of functions, the integrated circuit comprising: a plurality of heterogeneous computational elements; andan interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network changing interconnections between the plurality of heterogeneous computational elements in response to configuration information;wherein a first group of computational elements of the plurality of heterogeneous computational elements is allocated to form a plurality of functional units to perform a first function in parallel by changing interconnections in the interconnection network between the first group of heterogeneous computational elements;wherein a second group of computational elements of the plurality of heterogeneous computational elements is allocated to form a functional unit to perform a second function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements; andwherein the first group of heterogeneous computational elements allocated to at least one of the first functional units is reallocated to perform the second function by changing the interconnections between the group of heterogeneous computational elements of the at least one of the first functional units. 9. The adaptive computing integrated circuit of claim 8 one or more of the second group of heterogeneous computational elements are reconfigurable to form another functional unit to implement the first function. 10. The adaptive computing integrated circuit of claim 8 wherein if the second function is not currently used, the one or more of the second group of heterogeneous computational elements are reconfigurable by the interconnection network to implement a third function. 11. The adaptive computing integrated circuit of claim 10, wherein a third group of the heterogeneous computational elements is allocated to implement the third function. 12. The adaptive computing integrated circuit of claim 8, wherein some of first group of computational elements are reconfigured by changing the interconnections in the interconnection network to form a different version of a functional unit to perform the first function. 13. The adaptive computing integrated circuit of claim 12, wherein the different version of the functional unit is formed based on a parameter including decreased energy use, increase speed of performing the function or hardware availability. 14. The adaptive integrated circuit of claim 8, wherein the first and second functions are part of a sequential operation and wherein the one or more of the second group of heterogeneous computational elements is reconfigured to perform the second function after the first function is performed according to the configuration information. 15. A method for allocating hardware resources within an adaptive computing integrated circuit, comprising: in response to first configuration information, allocating a first group of computational elements of the plurality of heterogeneous computational elements to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements;allocating a second group of computational elements of the plurality of heterogeneous computational elements to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements; andreallocating at least some of the first group of heterogeneous computational elements allocated to the first functional unit to perform a second function by changing the interconnections between the first group of heterogeneous computational elements. 16. The method of claim 15, wherein the one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form one or more additional instances of the first version of the functional unit. 17. The method of claim 15, further comprising changing interconnections in the interconnection network to reallocate one or more of the first group of heterogeneous computational elements or one or more of the second group of heterogeneous computational elements to form a third version of a functional unit to perform the first function. 18. The method of claim 15, further comprising changing interconnections in the interconnection network to reallocate one or more of the second group of heterogeneous computational elements to implement a third function if the second function is not currently used. 19. The method of claim 15, further comprising configuring a third group of computational elements for a third function, wherein the third group of computational elements are used for one of functional units to perform the first function if the third function is not used. 20. The method of claim 15, wherein the first group of computational elements is reconfigured to the second version of the functional unit to perform the first function based on parameters including energy use, speed of performing the first function, or hardware availability. 21. The method of claim 15, wherein the first and second functions are part of a sequential operation and wherein the one or more of the second group of heterogeneous computational elements is reconfigured to perform the second function after the first function is performed.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (430)
Mani Meitav,Irit; Sarfati,Assaf, Accelerating responses to requests made by users to an internet.
Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
Benkeser Donald E. (Naperville IL) Cyr Joseph B. (Aurora IL) Greenberg Albert G. (Millburn NJ) Wright Paul E. (Basking Ridge NJ), Adaptive job scheduling for multiprocessing systems with master and slave processors executing tasks with opposite antic.
Bennett Toby D. ; Davis Donald J. ; Harris Jonathan C. ; Miller Ian D., Apparatus and method for constructing data for transmission within a reliable communication protocol by performing portions of the protocol suite concurrently.
Varga Steve ; Eagle ; III Bryan ; Desmarais Richard ; Cowling Robert ; Lemieux Michael D. ; Hall John, Apparatus and method for improved vending machine inventory maintenance.
Jerg Helmut,DEX ; Cerruti Daniele,ITX, Apparatus and method for repeated, automatic metering of precisely metered quantities of a powdered detergent into wate.
Roy Rupan, Apparatus and method of implementing systems on silicon using dynamic-adaptive run-time reconfigurable circuits for processing multiple, independent data and control streams of varying rates.
Master,Paul L.; Smith,Stephen J.; Watson,John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
Gelfer, George G.; Kampert, Werner; Kubatzki, Ralf; Thiel, Wolfgang, Arrangement and method for offering a message when loading service data for a terminal device.
Rejret Richard L. (Watertown WI) Rantanen William C. (Watertown WI) Weimer Michael G. (Oconomowoc WI) Parmley John W. (Watertown WI) Searing Lawrence G. (Nashotah WI) Powers Larry D. (Watertown WI), Automatic beverage dispenser.
Childs Matthew H. (Arlington TX) Norcross Thomas M. (Arlington TX), Automatic data generation for self-test of cryptographic hash algorithms in personal security devices.
Shannon Joseph W. (Kent OH) Ripley ; Jr. Clarence A. (Tallmadge OH) Dailey John Henry (Ravenna OH), Automatic drink dispensing apparatus having programming means.
Annese Clara Ann (Hamilton Square NJ) Basile Peter A. (Hudson OH) Colwell Dennis J. (East Windsor NJ) Shoaf Myron D. (Cranbury NJ), Beverage carbonation device.
McCann Gerald P. (7000 Macapa Dr. Los Angeles CA 90068) Verley Donald J. (43015 Lesina Dr. Lake Elizabeth CA 93532), Beverage dispenser for home or office.
Worley ; Jr. William S. (Saratoga CA) Bryg William R. (Saratoga CA) Baum Allen (Palo Alto CA), Cache memory consistency control with explicit software instructions.
Basile Peter A. (Hudson OH) Annese Clara Ann (Hamilton Square NJ) Colwell Dennis J. (East Windsor NJ), Carbonation chamber with sparger for beverage carbonation.
Hickman Paul L. (27140 Moody Rd. Los Altos Hills CA 94022) Stephens Lawrence K. (1250 Mildred Ave. San Jose CA 95125), Communication configurator and method for implementing same.
Martin Bryan R. ; Barraclough Keith, Communication interface between remote transmission of both compressed video and other data and data exchange with local peripherals.
Lewis Russell F. ; Shadowens Mark B. ; Deffner Gerhard Paul Heinrich ; Birdwell Gerald G., Communication system and methods for enhanced information transfer.
Thomas Gerard,FRX ; Lecomte Daniel,FRX ; Brignol Luc,FRX ; Christien Florence,FRX, Communications system and corresponding equipment for a subscriber installation.
Burmeister Curt K. (Somerville MA) Harris Kevin W. (Nashua NH) Noyce William B. (Hollis NH) Hobbs Steven O. (Westford MA), Compiler allocating a register to a data item used between a use and store of another data item previously allocated to.
Willis John Christopher ; Newshutz Robert Neill, Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models.
Webb Richard F. (Baltimore MD), Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal proce.
Kawan Joseph C. (Hollywood CA) Takata Melvin M. (Hermosa Beach CA) Samulon Alfred S. (Malibu CA) Parekh Dilip J. (Los Angeles CA) Marks Harvey (Canoga Park CA) Caruthers Douglas W. (Marina Del Rey CA, Computer and telephone apparatus with user friendly interface and enhanced integrity features.
James M. Crawford, Jr. ; Mukesh Dalal ; Joachim Paul Walser DE, Computer implemented scheduling system and process using abstract local search technique.
Sumimoto Shinji (Kawasaki JPX), Computer resource distributing method and system for distributing a multiplicity of processes to a plurality of computer.
Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.
Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
Scales ; III Hunter Ledbetter ; Diefendorff Keith Everett ; Olsson Brett ; Dubey Pradeep Kumar ; Hochsprung Ronald Ray ; Beavers Bradford Byron ; Burgess Bradley G. ; Snyder Michael Dean ; May Cathy , Data processing system for processing vector data and method therefor.
Butterfield Lee A ; Giallorenzi Thomas R ; Gibson ; Jr. L Andrew ; Griffin Dan M ; Harris Johnny M ; Perkins Steven B ; Steagall R William, Data scrambling system and method and communications system incorporating same.
Campbell Michael J. (Los Angeles CA) Finn Dennis J. (Los Angeles CA) Tucker George K. (Los Angeles CA) Vahey Michael D. (Manhattan Beach CA) Vedder Rex W. (Playa del Rey CA), Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and.
Blakeney ; II Robert D. (San Diego CA) Weaver ; Jr. Lindsay A. (Boulder CO) Ziv Noam A. (San Diego CA) Williamson Paul T. (San Diego CA) Padovani Roberto (San Diego CA), Demodulation element assignment in a system capable of receiving multiple signals.
Grube Gary W. (Palatine IL) Markison Timothy W. (Hoffman Estates ; IL), Detecting unauthorized modification of communication unit based on comparison between stored hardware identification cod.
Widergren Robert D. (Saratoga CA) Chen Wen-Hsiung (Sunnyvale CA) Fralick Stanley C. (Saratoga CA) Tescher Andrew G. (Claremont CA), Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback.
Pian Chao-Kuang (Anaheim CA) Nguyen Minh-Tram D. (Anaheim CA) Posch Theodore E. (Fullerton CA) Juhre Jeffrey E. (Arlington Heights IL), Distributed data driven process.
Ing-Simmons Nicholas K. (Oakley TX GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2), Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode.
DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
Santhanam Vatsa (Campbell CA), Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instruc.
Cohen Joshua L. ; Dean Cecil A. ; du Breuil Thomas L. ; Heer Daniel Nelson ; Maher David P. ; Poteat Vance Eugene ; Rance Robert John, Electronic identifiers for network terminal devices.
Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
Zinky, John A.; Schantz, Richard R.; Bakken, David E.; Loyall, Joseph P., Framework for providing quality of service requirements in a distributed object-oriented computer system.
Toms John Shackelford ; Brown Steven M. ; Miller William L. ; Weller George V. ; Russell Scott H. ; Branc Joseph R. ; Sweeton David C. ; Mikolajczak Matthew M., Furniture unit having a modular communication network.
Ravi Subramanian ; Keith Rieken ; Uma Jha ; David M. Holmes ; Joel D. Medlock ; Murali Krishnan, Generic finger architecture for spread spectrum applications.
Gaunt Loraine E. (Marietta GA) Crosby Samuel C. (Decatur GA) Saunders William J. (Stone Mountain GA) Bruffey ; Jr. Robert D. (Lilburn GA), Low-cost post-mix beverage dispenser and syrup supply system therefor.
Gaunt Loraine E. (Marietta GA) Crosby Samuel C. (Decatur GA) Saunders William J. (Stone Mountain GA) Bruffey ; Jr. Robert D. (Lilburn GA), Low-cost post-mix beverage dispenser and syrup supply system therefor.
Fuhrmann Amir Michael ; Rakib Selim Shlomo ; Azenkot Yehuda, Lower overhead method for data transmission using ATM and SCDMA over hybrid fiber coax cable plant.
Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Mapping requests from a processing unit that uses memory-mapped input-output space.
Odnert Daryl (Boulder Creek CA) Santhanam Vatsa (Sunnyvale CA), Method and apparatus for compiling computer programs with interprocedural register allocation.
Walton, Jay R.; Wallace, Mark; Ketchum, John W.; Howard, Steven J., Method and apparatus for processing data in a multiple-input multiple-output (MIMO) communication system utilizing channel state information.
Meng Wan-Yu,TWX ; Chang Cheng-Kai,TWX ; Chang Hwai-Tsu,TWX ; Hsu Fang-Ru,TWX ; Lee Ming-Rong,TWX, Method and apparatus for processing data in a neural network.
Bantz, David Frederick; Mastrianni, Steven J.; Mohindra, Ajay; Shea, Dennis G., Method and apparatus for providing automatic configuration of a computer system based on its physical location using an electronically read schedule.
Scholl Frederick W. (Riverdale NY) Coden Michael H. (New York NY), Method and apparatus for recovering data and clock information from a self-clocking data stream.
Bruce V. Schwartz ; Russell S. Greer ; Stephen S. Boyle ; Mark A. Fox ; Alain S. Rossmann ; Mark G. Lentczner ; Andrew L. Laursen ; Brad E. Sandman, Method and architecture for interactive two-way communication devices to interact with a network.
Bertolet Allan Robert ; Clinton Kim P.N. ; Gould Scott Whitney ; Keyser III Frank Ray ; Reny Timothy Shawn ; Zittritsch Terrance John, Method and system for layout and schematic generation for heterogeneous arrays.
Rechef Eran,ILX ; Raanan Gil,ILX ; Solan Eilon,ILX, Method and system for maintaining restricted operating environments for application programs or operating systems.
Fijolek John G. ; Beser Nurettin B., Method and system for providing quality-of-service in a data-over-cable system using configuration protocol messaging.
Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
Sven Wuytack BE; Francky Catthoor BE; Hugo De Man BE, Method for determining a storage bandwidth optimized memory organization of an essentially digital device.
Tiedemann ; Jr. Edward G. ; Holcman Alejandro Raul, Method for multi-mode handoff using preliminary time alignment of a mobile station operating in analog mode.
Grube Gary W. (Palatine IL) Markison Timothy W. (Hoffman Estates IL) Weston Thomas E. (Marengo IL), Method for reprogramming a communication unit\s access to a wireless communication system.
Wagner Ferdinand H. (24 Sterling Cir. ; Apt. 211 Wheaton IL 60187), Method of and apparatus for constructing a control system and control system created thereby.
Bennett Clay D. (Payson AZ) Holcomb Donald E. (Brooklyn Center MN) Kovar Henry C. (Brooklyn Park MN), Method of and apparatus for dispensing beverage into a tilted receptacle with automatic level responsive shut off.
Pechanek Gerald G. ; Revilla Juan Guillermo ; Barry Edwin F., Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor.
Thomas L. Drabenstott ; Gerald G. Pechanek ; Edwin F. Barry ; Charles W. Kurak, Jr., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.
Agrawal, Om P.; Sharpe-Geisler, Bradley A.; Chang, Herman M.; Nguyen, Bai; Tran, Giap H., Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources.
Budrovic, Martin T.; Kolson, David J., Methods, systems, and computer program products for compressing a computer program based on a compression criterion and executing the compressed program.
Harrison R. Loyd (Fullerton CA) Davies Steven P. (Ontario CA), Modular array processor architecture having a plurality of interconnected load-balanced parallel processing nodes.
Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Multi-processor having control over synchronization of processors in mind mode and method of operation.
Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD).
Gove Robert J. (Plano TX) Guttag Karl M. (Missouri City TX) Balmer Keith (Bedfordshire GB2) Ing-Simmons Nicholas K. (Bedfordshire GB2), Multi-processor with crossbar link of processors and memories and method of operation.
Austin ; deceased Forrest L. (late of Brooklyn Park MN) Willard executrix by Roberta A. (Mankato MN) Long Jerry A. (New Hope MN), Multiple flavor post-mix beverage dispensing head.
Barroso, Luiz A.; Gharachorloo, Kourosh; Nowatzyk, Andreas; Ravishankar, Mosur K.; Stets, Jr., Robert J., Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants.
Alpert Alan I. (Hopewell Junction NY) Greenstein Paul G. (Fishkill NY) Rodell John T. (Wappingers Falls NY) Raghayan Ramanathan (Austin TX), Optimizing assembled code for execution using execution statistics collection, without inserting instructions in the cod.
Gifford David K. (Cambridge MA), Parallel processing system with processor array and network communications system for transmitting messages of variable.
Bishop Chapman Brock ; Eli Chiprout ; Elmootazbellah Nabil Elnozahy ; David Brian Glasco ; Ramakrishnan Rajamony ; Freeman Leigh Rawson, III ; Ronald Lynn Rockhold, Performance monitoring in a NUMA computer.
Urban G. Daniel (Silver Spring MD) McCarthy Robert (Arlington VA) Schuchman David (Rockville MD) Bruno Ronald (Arlington VA), Position enhanced cellular telephone system.
Sedam Jason K. (Dunwoody GA) Fuerst William R. (Tucson AZ), Post-mix beverage dispensing system syrup package, valving system, and carbonator therefor.
Mohamed Moataz A. ; Spence John R. ; Malich Kenneth W., Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks.
Chiarulli Donald M. (4724 Newcomb Dr. Baton Rouge LA 70808) Rudd W. G. (Dept. of Computer Science Oregon State University Corvallis OR 97331) Buell Duncan A. (1212 Chippenham Dr. Baton Rouge LA 70808, Processor utilizing reconfigurable process segments to accomodate data word length.
Dabbish Ezzat A. (Buffalo Grove IL) Puhl Larry C. (Sleepy Hollow IL) Brendle William L. (Carol Stream IL), Programmable array logic self-checking system.
Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array.
Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array with bus repeaters.
Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device with hierarchical confiquration and state storage.
Mohamed Moataz Ali, Programming a vector processor and parallel programming of an asymmetric dual multiprocessor comprised of a vector processor and a risc processor.
Hinedi Sami M. ; Griep Karl R. ; Million Samson, Punctured serial concatenated convolutional coding system and method for low-earth-orbit satellite data communication.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
Hung, Ching-Yu; Estevez, Leonardo W.; Rabadi, Wissam A., Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing).
Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford GB2) Guttag Karl M. (Missouri City TX), Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of.
Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining proc.
Metcalfe L. D. (Royalton Township ; Berrien County MI) Maczuzak Michael J. (Southfield MI) Bailey Curtis J. (Birmingham MI) Deyo Paul R. (Van Buren Township ; Wayne County MI), Refrigerator door structure.
Cherry David N. (Louisville KY) Haynes Gary L. (Louisville KY) Virgin Stephen P. (Louisville KY), Refrigerator with door mounted dispenser supply mechanism.
Karen W. Halford ; Gayle Patrick Martin ; Julian Bartow Willingham ; Mark A. Webster ; Gregory S. Sinclair, Selective modification of antenna directivity pattern to adaptively cancel co-channel interference in TDMA cellular communication system.
Macias Nicholas J. ; Henry ; III Lawrence B. ; Raju Murali Dandu, Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells.
Howard, Michael L.; Harper, Jr., William R., Service provider for providing data, applications and services to embedded devices and for facilitating control and monitoring of embedded devices.
Shaw Venson M. (111 Reldyes Ave. Leonia NJ 07605) Shaw Steven M. (111 Reldyes Ave. Leonia NJ 07605), Single chip integrated circuit system architecture for document installation set computing.
Gove Robert J. ; Balmer Keith,GBX ; Ing-Simmons Nicholas Kerin,GBX ; Guttag Karl Marion, Single integrated circuit embodying a risc processor and a digital signal processor.
Assis Mascarenhas de Oliveira Carlos Henrique (Sao Paulo BRX) Bruno Leonardo (Sao Paulo BRX) Padilla Julio Roberto (Sao Paulo BRX) Maselli Alberto (Sao Paulo BRX) Moraes Mesiano Ivan Jeronimo (Sao Pa, Soda dispensing machine.
Balmer Keith (6 Salcombe Close Bedford (Bedfordshire) GB2 MK40 38A) Ing-Simmons Nicholas K. (74 Lincroft ; Oakley Bedford (Bedfordshire) TX GB2 MK43 7SS) Guttag Karl M. (4015 S. Sandy Ct. Missouri Ci, Switch matrix having integrated crosspoint logic and method of operation.
Jourdenais Karen C. (Concord MA) Frankel James L. (Lexington MA) Goldhaber Steven N. (Boulder CO) Seamonson Linda J. (Wellesley MA), System and method for compiling a source code supporting data parallel variables.
Hendrickson, Keith; Maguy, William; Prehn, Paul; Stamos, Nick; Su, Annie, System and method for measuring wireless device and network usage and performance metrics.
Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
Bimm, Mike Steven; Clark, Douglas Patrick; Kleinbach, Steven John; Tory, Daniel Charles; Custeau, Randall David; Russell, Robert Joseph; Cai, Yueqiang, System and method for universal service activation.
Gove Robert J. ; Balmer Keith,GBX ; Ing-Simmons Nicholas Kerin,GBX ; Guttag Karl Marion, System and method of memory access in apparatus having plural processors and plural memories.
Taylor Brad (Oakland CA) Dowling Robert (Albany CA), System for compiling algorithmic language source code for implementation in programmable hardware.
De Oliveira Kastrup Pereira, Bernardo; Bink, Adrianus J.; Hoogerbrugge, Jan, System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time.
Enelow Michael R. (Miami Lakes FL) Levy Michael (Plantation FL) Porter William P. (Coral Springs FL), System for indicating and controlling dispensing of beverages.
Wichter Martin A. (Arlington TX) Pohrte Tom R. (The Colony TX) Ross Jack A. (The Colony TX) Sadler Ray G. (Plano TX), System for managing multiple dispensing units and method of operation.
Cantone Michael R. (Westfield NJ) Woo Nam-Sung (New Providence NJ), System for synthesizing field programmable gate array implementations from high level circuit descriptions.
Albrecht Alain,FRX ; Fleurisson Marc,FRX ; Gibello Pierre-Yves,FRX ; Richoux Bruno,FRX ; Sehabiague Bruno,FRX, System using designer editor and knowledge base for configuring preconfigured software in an open system in a distribute.
Simons Barbara Bluestein ; Sarkar Vivek, System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by th.
Ainsworth,Scott G.; Hawkins,Charles F.; Plaster,Donald J., Systems and methods for obtaining digital signatures on a single authoritative copy of an original electronic record.
Ginter Karl L. ; Shear Victor H. ; Sibert W. Olin ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
Ginter, Karl L.; Shear, Victor H.; Spahn, Francis J.; Van Wie, David M., Systems and methods for secure transaction management and electronic rights protection.
Tam Ulrica ; Berl Steven H., Technique for capturing information needed to implement transmission priority routing among heterogeneous nodes of a computer network.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
Gove Robert J. (Plano TX) Guttag Karl Marion (Missouri City TX) Balmer Keith (Bedford GBX) Ing-Simmons Nicholas Kerin (Bedford GBX), Unique processor identifier in a multi-processing system having plural memories with a unified address space correspondi.
Kolls, H. Brock, Universal interactive advertising and payment system network for public access electronic commerce and business related products and services.
Coons, Thomas L; Getler, Robert M; Landry, R Kent; Rogers, Steven B, Usage-based billing and management system and method for printers and other assets.
Wheeler James E. (Schenectady NY) Hardy Robert M. (Scotia NY) Dunki-Jacobs Robert J. (Saratoga NY) Premerlani William J. (Scotia NY), VLSI programmable digital signal processor.
Sugahara Takayuki,JPX ; Suzuki Junzo,JPX ; Kobari Harukuni,JPX, Variable length coded data processing method and device for performing the same method.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.