[특허]Electronic interconnect devices having conductive vias

Tyco Electronics Corporation

검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
검색연산자

검색도움말
검색연산자	기능	검색시 예
()	우선순위가 가장 높은 연산자	예1) (나노 (기계 \| machine))
공백	두 개의 검색어(식)을 모두 포함하고 있는 문서 검색	예1) (나노 기계) 예2) 나노 장영실
\|	두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색	예1) (줄기세포 \| 면역) 예2) 줄기세포 \| 장영실
!	NOT 이후에 있는 검색어가 포함된 문서는 제외	예1) (황금 !백금) 예2) !image
*	검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색	예) semi*
""	따옴표 내의 구문과 완전히 일치하는 문서만 검색	예) "Transform and Quantization"

과학기술 지식인프라 ScienceON

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

특허 상세정보

MyON담기

내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Electronic interconnect devices having conductive vias

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01R-013/648 H01R-013/658 H01R-012/71 H01R-013/24 H01R-024/38
미국특허분류(USC)	439/607.09;
출원번호	US-0769584 (2013-02-18)
등록번호	US-9039448 (2015-05-26)
발명자 / 주소	Mason, Jeffery Walter Alden, III, Wayne Stewart
출원인 / 주소	Tyco Electronics Corporation
인용정보	피인용 횟수 : 4 인용 특허 : 18

초록

An electronic interconnect device includes a substrate having a first surface and a second surface. The substrate has a plurality of openings extending between the first and second surfaces. Each opening has a conductive outer via, an insulative barrier and a conductive inner via. The outer via, insulative barrier and inner via are concentric within the opening such that the insulating barrier is disposed between the conductive inner via and the conductive outer via. The conductive inner via is configured to receive a conductor to be inserted therein.

대표
청구항
▼

1. An electronic interconnect device comprising: a substrate having a first surface and a second surface, the substrate having a plurality of openings extending between the first and second surfaces, each opening having a conductive outer via, an insulative barrier deposited on the conductive outer via, and a conductive inner via deposited on the insulative barrier, wherein the conductive outer via, insulative barrier and conductive inner via are concentric within the opening such that the insulating barrier is disposed between the conductive inner via and the conductive outer via; andwherein the conductive inner via defines an open space of the opening configured to receive a conductor to be inserted therein. 2. The electronic interconnect device of claim 1, wherein a plurality of the conductive outer vias are electrically commoned and grounded. 3. The electronic interconnect device of claim 1, further comprising a ground shield on the substrate, the outer vias being electrically common with the ground shield. 4. The electronic interconnect device of claim 1, wherein the substrate is plated with a ground plating on the first surface and in the plurality of openings, the ground plating defining a ground shield on the first surface and defining the conductive outer vias in the openings, each of the outer vias being electrically commoned by the ground shield. 5. The electronic interconnect device of claim 1, wherein the insulative barriers are coated on the corresponding conductive outer vias and the conductive inner vias are plated on the corresponding insulative barriers. 6. The electronic interconnect device of claim 1, further comprising conductors received in the openings and being electrically connected to the conductive inner vias, the conductors transmitting data signals to the conductive inner vias. 7. The electronic interconnect device of claim 1, wherein the conductive outer vias are electrically connected to a ground layer on the first surface, the insulative barriers being integral with an insulative layer deposited on the ground layer. 8. The electronic interconnect device of claim 1, wherein the insulative barriers are integral with an insulative layer deposited on the second surface, the conductive inner vias being electrically connected to solder pads deposited on the insulative layer, solder balls being applied to corresponding signal pads. 9. The electronic interconnect device of claim 1, wherein the substrate further comprises at least one grounding opening therethrough consisting of a conductive ground via electrically connected to the conductive outer vias, each ground opening being devoid of any insulative barrier and any conductive inner via. 10. An electronic interconnect device comprising: a substrate having a first surface and a second surface, the substrate having a plurality of openings extending between the first and second surfaces, each opening having a conductive outer via, an insulative barrier deposited on the conductive outer via, and a conductive inner via deposited on the insulative barrier, wherein the conductive outer via, insulative barrier and conductive inner via are concentric within the opening such that the insulative barrier is disposed between the conductive inner via and the conductive outer via, wherein the conductive inner via defines an open space configured to receive a conductor to be inserted therein; anda plurality of conductors received in corresponding conductive inner vias, the conductors being electrically connected to the conductive inner via, the conductors having a first end extending out of the openings and being configured to be electrically connected to a first electronic component. 11. The electronic interconnect device of claim 10, wherein the plurality of conductors are compressive in a longitudinal direction along corresponding opening axes. 12. The electronic interconnect device of claim 10, wherein the plurality of conductors are deflectable in a vertical direction into the openings, the plurality of conductors being deflectable in a horizontal direction to press outward against the inner vias. 13. The electronic interconnect device of claim 10, wherein the plurality of conductors are compressible to shorten and widen the conductors within the openings, the conductors being biased against the conductive inner vias. 14. The electronic interconnect device of claim 10, wherein each conductor comprises a spring and an arrowhead spring extending from the spring and defining the first end, the arrowhead spring having a tip configured to engage the first electronic component, the arrowhead spring being narrower proximate the tip and wider toward the spring. 15. The electronic interconnect device of claim 14, wherein the spring compresses vertically to shorten the conductor, the arrowhead spring deflects outward to widen the conductor and press outward against the conductive inner via. 16. The electronic interconnect device of claim 10 further comprising a cover on the first surface, the cover capturing the conductors in the openings, the conductors being spring biased against toward the cover. 17. The electronic interconnect device of claim 10, wherein the conductors comprise elastomeric columns being internally conductive, the elastomeric column being compressible and pressed outward against the conductive inner vias to define electrical paths between the elastomeric columns and the conductive inner vias. 18. The electronic interconnect device of claim 10, wherein the conductors each have a second end extending out of the openings beyond the second surface, the second ends being configured to be electrically connected to a second electronic component, wherein electrical paths are defined between the first and second electronic components through the conductors and the conductive inner vias. 19. The electronic interconnect device of claim 10, wherein the insulative barriers are integral with an insulative layer deposited on the second surface, the conductive inner vias being electrically connected to signal pads deposited on the insulative layer, solder balls being applied to corresponding signal pads, wherein electrical paths are defined from the first end of the conductor to the conductive inner vias and from the conductive inner vias to the signal pads and solder balls. 20. An electronic interconnect system comprising: a substrate having a first surface and a second surface, the substrate having a plurality of openings extending between the first and second surfaces, each opening having a conductive outer via, an insulative barrier deposited on the conductive outer via, and a conductive inner via deposited on the insulative barrier, wherein the conductive outer via, insulative barrier and conductive inner via are concentric within the opening such that the insulative barrier is disposed between the conductive inner via and the conductive outer via, wherein the conductive inner via defines an open space configured to receive a conductor to be inserted therein and electrically connected to the conductive inner via; andan electrical connector having a plurality of conductive compliant pins extending therefrom, the compliant pins comprising the conductors that provide electrical connections with the conductive inner vias, when the electrical connector is mated to the substrate at the first surface such that the compliant pins extend into corresponding openings to engage corresponding conductive inner vias.

인용문헌 (18)

이 특허를 인용한 특허 (4)

IPC 상위 출원인

내보내기

상세정보
내보내기 구분	파일저장 인쇄 메일전송
구성항목	관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	> 총 건의 자료가 검색되었습니다. > 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) > 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. > 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) > 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오 > ~ > Text(ASCII format) Excel format

과학기술 지식인프라 ScienceON

ScienceON Chatbot

연합인증

특허 상세정보

Electronic interconnect devices having conductive vias

초록

대표
청구항
▼

인용문헌 (18)

이 특허를 인용한 특허 (4)

IPC 상위 출원인

과제정보

상세정보조회

원문조회

IPC 상세정보(version : 201201)

연구과제 성과물(0)

참여연구원의 다른 문헌(0)

처리중입니다.

잠시만 기다려주세요.

ScienceON Chatbot

연합인증

특허 상세정보

Electronic interconnect devices having conductive vias

초록

대표청구항 ▼

인용문헌 (18)

이 특허를 인용한 특허 (4)

IPC 상위 출원인

과제정보

상세정보조회

원문조회

IPC 상세정보(version : 201201)

연구과제 성과물(0)

참여연구원의 다른 문헌(0)

처리중입니다.

잠시만 기다려주세요.

대표
청구항
▼