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다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0903470 (2013-05-28) |
등록번호 | US-9047440 (2015-06-02) |
우선권정보 | WO-PCT/EP00/10516 (2000-10-09); DE-101 10 530 (2001-03-05); DE-101 11 014 (2001-03-07); DE-101 35 210 (2001-07-24); DE-101 35 211 (2001-07-24); DE-101 39 170 (2001-08-16); DE-101 42 231 (2001-08-29); DE-101 42 894 (2001-09-03); DE-101 42 903 (2001-09-03); DE-101 42 904 (2001-09-03); DE-101 44 732 (2001-09-11); DE-101 44 733 (2001-09-11); DE-101 45 792 (2001-09-17); DE-101 45 795 (2001-09-17); DE-101 46 132 (2001-09-19); WO-PCT/EP01/11299 (2001-09-30) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 5 인용 특허 : 558 |
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
1. A data processor on a chip comprising: a plurality of processing array elements disposed in a multi-dimensional array, the processing array elements including a plurality of data processing units comprising arithmetic logic units operative to perform one or more of a plurality of arithmetic opera
1. A data processor on a chip comprising: a plurality of processing array elements disposed in a multi-dimensional array, the processing array elements including a plurality of data processing units comprising arithmetic logic units operative to perform one or more of a plurality of arithmetic operand functions and a plurality of memory units in operative communication with the plurality of arithmetic logic units, wherein the data processing units within a first axis of the multi-dimensional array are in communication with the memory units within the first axis of the multi-dimensional array;at least one interface unit operative to provide at least one communication channel between the plurality of processing array elements;a bus system flexibly interconnecting the plurality of processing array elements for multi-directional communication across the bus system among the plurality of processing array elements. 2. The data processor of claim 1, wherein the multi-dimensional array is a two dimensional array, the first axis being a horizontal axis and a second axis, the second axis being a vertical axis. 3. The data processor of claim 1, wherein the multi-dimensional array is a three dimensional array, the first axis being different from a second axis, the first axis and the second axis each being at least one of an X axis, a Y axis and a Z axis. 4. The data processor of claim 1, wherein the bus system includes: a first structure dedicated for data transfer in the first axis; anda second structure dedicated for data transfer in a second axis. 5. The method of claim 4, wherein the bus system further includes at least one secondary bus path providing communication between a plurality of the processing array elements. 6. The method of claim 5, wherein the at least one secondary bus path comprises at least one first-in-first-out buffer for transferring data. 7. The method of claim 1, wherein the bus system supports transmission of at least 32-bit wide data. 8. The method of claim 1, wherein the bus system supports transmission of at least 64-bit wide data. 9. The method of claim 1, wherein the at least one interface unit transfers data between the data processor and an external memory in packets. 10. The method of claim 1, wherein the at least one interface unit supports a plurality of data processor internal data channels. 11. A data processor on a chip comprising: a plurality of processing array elements disposed in a multi-dimensional array, the processing array elements including a plurality of arithmetic logic units operative to perform one or more of a plurality of arithmetic operand functions and a plurality of memory units in operative communication with the plurality of arithmetic logic units;at least one interface unit operative to provide at least one communication channel between the plurality of processing array elements;a bus system flexibly interconnecting the plurality of processing array elements for multi-directional communication across the bus system among the plurality of processing array elements.
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