Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is rece
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
대표청구항▼
1. A semiconductor device, comprising a conductive interconnect feature connecting a first conductive feature with a second conductive feature, the conductive interconnect feature passing through a conformal intervening layer and partially landing on the first conductive feature, wherein the unlande
1. A semiconductor device, comprising a conductive interconnect feature connecting a first conductive feature with a second conductive feature, the conductive interconnect feature passing through a conformal intervening layer and partially landing on the first conductive feature, wherein the unlanded portion of the conductive interconnect feature rests on but does not penetrate the conformal intervening layer. 2. The device of claim 1 wherein the conformal intervening layer conforms to a protruding portion of the first conductive feature that extends beyond an insulator layer. 3. The device of claim 1, wherein the first conductive feature is included in a first insulator layer, and the second conductive feature is included in a second insulator layer, and the first insulator layer, conformal intervening layer, and second insulator layer are arranged in a stack. 4. The device of claim 1, wherein a protruding portion of the first conductive feature extends beyond an insulator layer, the protruding portion having a rounded corner with which the conductive interconnect feature connects. 5. The device of claim 1, wherein the first conductive feature is included in a first insulator layer, and the ratio of first insulator layer etch rate to the first conductive feature etch rate for a given etch process is greater than 3. 6. The device of claim 1, wherein a portion of the first conductive feature at least partially protrudes from a first insulator layer, and the conformal intervening layer is at least partially on and conforms to the protruding portion. 7. The device of claim 6, further comprising an additional insulator layer at least partially on the conformal intervening layer, wherein the conductive interconnect feature further passes through the additional insulator layer. 8. The device of claim 7, wherein the additional insulator layer comprises a flowable dielectric material. 9. The device of claim 8, wherein the flowable dielectric material is one of a flowable carbide or flowable nitride. 10. The device of claim 1, wherein the first conductive feature is included in a first insulator layer, and the second conductive feature is included in a second insulator layer, and at least one of the first and second insulator layers comprises an ultra-low dielectric material having a dielectric constant below that of silicon dioxide, and the conformal intervening layer comprises a dielectric material having a higher dielectric constant than the ultra-low dielectric material. 11. A mobile computing system comprising the device of claim 1. 12. A microprocessor comprising the device of claim 1. 13. A memory circuit comprising the device of claim 1. 14. A semiconductor structure, comprising: a first insulator layer having a first conductive feature;a second insulator layer having a second conductive feature protruding therefrom;a conformal dielectric layer at least partially on and conforming to the protruding portion of the second conductive feature; anda conductive interconnect feature connecting the first conductive feature with the second conductive feature, the conductive interconnect feature passing through the conformal dielectric layer and partially landing on the second conductive feature so as to provide an unlanded portion of the conductive interconnect feature, wherein the unlanded portion of the conductive interconnect feature rests on but does not penetrate the conformal intervening layer. 15. The structure of claim 14, wherein the first insulator layer, conformal dielectric layer, and second insulator layer are arranged in a stack. 16. The structure of claim 14, wherein the protruding portion of the second conductive feature has a rounded corner with which the conductive interconnect feature connects. 17. The structure of claim 14, wherein the ratio of first insulator layer etch rate to the first conductive feature etch rate for a given etch process is greater than 3. 18. A semiconductor structure, comprising: a conductive interconnect feature connecting a first conductive feature with a second conductive feature, the conductive interconnect feature passing through a conformal dielectric layer and partially landing on the first conductive feature so as to provide an unlanded portion of the conductive interconnect feature, wherein the unlanded portion of the conductive interconnect feature rests on but does not penetrate the conformal intervening layer; andan insulator layer at least partially on the conformal dielectric layer, wherein the conductive interconnect feature further passes through the insulator layer. 19. The structure of claim 18, wherein the additional insulator layer comprises a flowable dielectric material. 20. The structure of claim 19, wherein the flowable dielectric material is one of a flowable carbide or flowable nitride.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (50)
Chooi Simon,SGX ; Zhou Mei-Sheng,SGX ; Xu Yi,SGX, Air bridge process for forming air gaps.
Buchwalter, Leena P.; Callegari, Alessandro Cesare; Cohen, Stephan Alan; Graham, Teresita Ordonez; Hummel, John P.; Jahnes, Christopher V.; Purushothaman, Sampath; Saenger, Katherine Lynn; Shaw, Jane, Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same.
Colgan Evan George ; Rodbell Kenneth Parker ; Totta Paul Anthony ; White James Francis, Interconnect structure using Al.sub.2 Cu for an integrated circuit chip.
Gaw Eng T. ; Vu Quat T. ; Fraser David B. ; Chiang Chien ; Young Ian A. ; Marieb Thomas N. D., Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer.
Moon Yong Tae,KRX ; Kim Dong Joon,KRX ; Song Keun Man,KRX ; Park Seong Ju,KRX, Method for fabricating white light emitting diode using InGaN phase separation.
Boeck Bruce Allen ; Wetzel Jeff Thomas ; Sparks Terry Grant, Method for manufacturing a low dielectric constant inter-level integrated circuit structure.
Hwang, Min Wook, Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby.
Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Bandyopadhyay Basab ; Michael Mark W. ; Brennan William S., Method of formation of an air gap within a semiconductor dielectric by solvent desorption.
Stoltz Richard A. (Plano TX) Tigelaar Howard (Allen TX) Cho Chih-Chen (Richardson TX), Method of forming air gap dielectric spaces between semiconductor leads.
Colburn,Matthew E; Dalton,Timothy J; Huang,Elbert; Karecki, legal representative,Anna; Nitta,Satya V; Purushothaman,Sampath; Saenger,Katherine L; Surendra,Maheswaran; Karecki,Simon M, Method of forming closed air gap interconnects and structures formed thereby.
Ito Nobukazu,JPX ; Matsubara Yoshihisa,JPX, Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface.
Beilin Solomon I. ; Chou William T. ; Lee Michael G. ; Ngo David Dung ; Peters Michael G. ; Roman James J. ; Takahashi Yasuhito, Power conducting substrates with high-yield integrated substrate capacitor.
Ueda,Tetsuya, Semiconductor device with an air gap between lower interconnections and a connection portion to the lower interconnections not formed adjacent to the air gap.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.