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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0653639 (2012-10-17) |
등록번호 | US-9075605 (2015-07-07) |
우선권정보 | DE-101 10 530 (2001-03-05); DE-101 11 014 (2001-03-07); WO-PCT/EP01/06703 (2001-06-13); DE-101 29 237 (2001-06-20); EP-01115021 (2001-06-20); DE-101 35 210 (2001-07-24); DE-101 35 211 (2001-07-24); WO-PCT/EP01/08534 (2001-07-24); DE-101 39 170 (2001-08-16); DE-101 42 231 (2001-08-29); DE-101 42 894 (2001-09-03); DE-101 42 903 (2001-09-03); DE-101 44 732 (2001-09-11); DE-101 42 904 (2001-09-13); DE-101 45 792 (2001-09-17); DE-101 45 795 (2001-09-17); DE-101 46 132 (2001-09-19); WO-PCT/EP01/11299 (2001-09-30); DE-101 54 259 (2001-11-05); DE-101 54 260 (2001-11-05); DE-101 44 733 (2001-11-09); EP-01129923 (2001-12-14); EP-02001331 (2002-01-18); DE-102 02 044 (2002-01-19); DE-102 02 175 (2002-01-20); DE-102 06 653 (2002-02-15); DE-102 06 856 (2002-02-18); DE-102 06 857 (2002-02-18); DE-102 07 224 (2002-02-21); DE-102 07 225 (2002-02-21); DE-102 07 226 (2002-02-21); DE-102 08 434 (2002-02-27); DE-102 08 435 (2002-02-27) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 0 인용 특허 : 601 |
A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselect
A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.
1. A method for operating a multiprocessor system comprising a plurality of data processing cells, each of the plurality of data processing units (a) including at least one Arithmetic Logic Unit (ALU) and a register unit and (b) being adapted for sequentially processing data, the method comprising:
1. A method for operating a multiprocessor system comprising a plurality of data processing cells, each of the plurality of data processing units (a) including at least one Arithmetic Logic Unit (ALU) and a register unit and (b) being adapted for sequentially processing data, the method comprising: the multiprocessor system setting a clock frequency, of at least a part of the multiprocessor system to a minimum in accordance with a number of pending operations of a first processor;the multiprocessor system subsequently increasing the clock frequency of the at least the part of the multiprocessor system to a maximum in accordance with a number of pending operations of a second processor; andthe multiprocessor system subsequently reducing the clock frequency of the at least the part of the multiprocessor system in accordance with (a) an operating temperature threshold preventing over-temperature and (b) a hysteresis characteristic. 2. The method of claim 1 wherein: said clock frequency is determined in part by processor voltage. 3. The method of claim 1 wherein: said clock frequency is determined in part by available power. 4. The method of claim 1 wherein: said clock frequency is determined in part by a user setting. 5. The method of claim 1 wherein: said clock frequency is determined in part by available power and a user setting. 6. The method of claim 1 wherein: said number of pending operations is determined at by the fill level of one or more buffers.
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