초록 ▼

Embodiments disclosed include variable amplitude signal generators for generating a sinusoidal signal having limited direct current (DC) offset variation and related devices and methods. Instead of employing a single pulse width modulation (PWM) signal to generate a sinusoidal signal, in one embodim

Embodiments disclosed include variable amplitude signal generators for generating a sinusoidal signal having limited direct current (DC) offset variation and related devices and methods. Instead of employing a single pulse width modulation (PWM) signal to generate a sinusoidal signal, in one embodiment, a circuit is provided that generates two PWM signals. The first PWM signal is a high-to-low PWM signal, where the active state is a lower signal level. The second PWM signal is a low-to-high PWM signal where active state is a higher signal level. The first and second PWM signals are combined to provide a summed signal, which is filtered to generate a sinusoidal signal. The DC offset of the first PWM signal varies inversely to the DC offset of the second PWM signal. In this manner, distortions caused by variations in the DC offset present in the generated sinusoidal signal are limited (i.e., reduced or eliminated).

대표청구항 ▼

1. A variable amplitude signal generator for generating a sinusoidal signal having limited DC offset variation, comprising: a circuit configured to: generate a first PWM signal, wherein the first PWM signal is a high-to-low PWM signal;generate a second PWM signal, wherein the second PWM signal is a

1. A variable amplitude signal generator for generating a sinusoidal signal having limited DC offset variation, comprising: a circuit configured to: generate a first PWM signal, wherein the first PWM signal is a high-to-low PWM signal;generate a second PWM signal, wherein the second PWM signal is a low-to-high PWM signal out of phase with the first PWM signal;a combiner node configured to receive the first PWM signal and the second PWM signal, and combine the first PWM signal and the second PWM signal into a summed signal; anda filter configured to receive the summed signal, and filter the received summed signal into a sinusoidal signal having limited DC offset variation,wherein the circuit is configured to generate the second PWM signal a half cycle out of phase with the first PWM signal. 2. A variable amplitude signal generator for generating a sinusoidal signal having limited DC offset variation, comprising: a circuit configured to: generate a first PWM signal, wherein the first PWM signal is a high-to-low PWM signal;generate a second PWM signal, wherein the second PWM signal is a low-to-high PWM signal out of phase with the first PWM signal;a combiner node configured to receive the first PWM signal and the second PWM signal, and combine the first PWM signal and the second PWM signal into a summed signal; anda filter configured to receive the summed signal, and filter the received summed signal into a sinusoidal signal having limited DC offset variation,wherein the circuit is further configured to generate the first PWM signal having a first duty cycle, and further configured to generate the second PWM signal having a second duty cycle equal or substantially equal to the first duty cycle, andwherein the circuit is further configured to vary the first duty cycle of the first PWM signal from a lower percentage to a higher percentage, and further configured to vary the second duty cycle of the second PWM signal from the lower percentage to the higher percentage. 3. The signal generator of claim 2, wherein the circuit is further configured to vary the first duty cycle of the first PWM signal up to 50%, and further configured to vary the second duty cycle of the second PWM signal up to 50%. 4. The signal generator of claim 2, wherein the circuit is further configured to vary the first duty cycle of the first PWM signal up to 100%, and further configured to vary the second duty cycle of the second PWM signal up to 100%. 5. A variable amplitude signal generator for generating a sinusoidal signal having limited DC offset variation, comprising: a circuit configured to: generate a first PWM signal, wherein the first PWM signal is a high-to-low PWM signal;generate a second PWM signal, wherein the second PWM signal is a low-to-high PWM signal out of phase with the first PWM signal;a combiner node configured to receive the first PWM signal and the second PWM signal, and combine the first PWM signal and the second PWM signal into a summed signal;a filter configured to receive the summed signal, and filter the received summed signal into a sinusoidal signal having limited DC offset variation;a first resistor configured to receive the first PWM signal from the circuit; anda second resistor configured to receive the second PWM signal from the circuit;wherein the combiner node is configured to receive the first PWM signal from the first resistor and the second PWM signal from the second resistor, and combine the first PWM signal and the second PWM signal into a summed signal. 6. A variable amplitude signal generator for generating a sinusoidal signal having limited DC offset variation, comprising: a circuit configured to: generate a first PWM signal, wherein the first PWM signal is a high-to-low PWM signal;generate a second PWM signal, wherein the second PWM signal is a low-to-high PWM signal out of phase with the first PWM signal;a combiner node configured to receive the first PWM signal and the second PWM signal, and combine the first PWM signal and the second PWM signal into a summed signal; anda filter configured to receive the summed signal, and filter the received summed signal into a sinusoidal signal having limited DC offset variation,wherein the circuit is further configured to generate the first PWM signal having a first duty cycle, and further configured to generate the second PWM signal having a second duty cycle equal or substantially equal to the first duty cycle, andwherein the circuit is configured to generate the first PWM signal having the first duty cycle based on a first duty cycle sequence stored in a look-up table in memory, and generate the second PWM signal having the second duty cycle based on a second duty cycle sequence stored in a look-up table in memory. 7. A method of generating a sinusoidal signal having limited DC offset variation, comprising: generating a first PWM signal, wherein the first PWM signal is a high-to-low PWM signal;generating a second PWM signal, wherein the second PWM signal is a low-to-high PWM signal out of phase with the first PWM signal;combining the first PWM signal and the second PWM signal into a summed signal; andfiltering the summed signal into a sinusoidal signal having limited DC offset variation,wherein generating the second PWM signal further comprises generating the second PWM signal, wherein the second PWM signal is out of phase with the first PWM signal by a half cycle. 8. A method of generating a sinusoidal signal having limited DC offset variation, comprising: generating a first PWM signal, wherein the first PWM signal is a high-to-low PWM signal;generating a second PWM signal, wherein the second PWM signal is a low-to-high PWM signal out of phase with the first PWM signal;combining the first PWM signal and the second PWM signal into a summed signal; andfiltering the summed signal into a sinusoidal signal having limited DC offset variation,wherein the generating the first PWM signal further comprises generating the first PWM signal having a first duty cycle, and generating the second PWM signal further comprises generating the second PWM signal having a second duty cycle equal or substantially equal to the first duty cycle, andwherein generating the first PWM signal further comprises varying the first duty cycle of the first PWM signal from a lower percentage to a higher percentage, and generating the second PWM signal further comprises varying the second duty cycle of the second PWM signal from the lower percentage to the higher percentage. 9. The method of claim 8, wherein generating the first PWM signal further comprises varying the first duty cycle of the first PWM signal up to 50%, and generating the second PWM signal further comprises varying the second duty cycle of the second PWM signal up to 50%. 10. The method of claim 8, wherein generating the first PWM signal further comprises varying the first duty cycle of the first PWM signal up to 100%, and generating the second PWM signal further comprises varying the second duty cycle of the second PWM signal up to 100%. 11. A method of generating a sinusoidal signal having limited DC offset variation, comprising: generating a first PWM signal, wherein the first PWM signal is a high-to-low PWM signal;generating a second PWM signal, wherein the second PWM signal is a low-to-high PWM signal out of phase with the first PWM signal;combining the first PWM signal and the second PWM signal into a summed signal; andfiltering the summed signal into a sinusoidal signal having limited DC offset variation,wherein generating the first PWM signal further comprises retrieving the first PWM signal from a memory and generating the second PWM signal further comprises retrieving the second PWM signal from the memory.