Method and system for implementing fragment operation processing across a graphics bus interconnect
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-013/14
G06F-015/16
G06F-003/12
출원번호
US-0253875
(2005-10-18)
등록번호
US-9092170
(2015-07-28)
발명자
/ 주소
Danskin, John M.
Tamasi, Anthony Michael
출원인 / 주소
NVIDIA CORPORATION
인용정보
피인용 횟수 :
0인용 특허 :
199
초록▼
A method and system for a cooperative graphics processing across a graphics bus in a computer system. The system includes a bridge coupled to a system memory via a system memory bus and coupled to a graphics processor via the graphics bus. The bridge includes a fragment processor for implementing co
A method and system for a cooperative graphics processing across a graphics bus in a computer system. The system includes a bridge coupled to a system memory via a system memory bus and coupled to a graphics processor via the graphics bus. The bridge includes a fragment processor for implementing cooperative graphics processing with the graphics processor coupled to the graphics bus. The fragment processor is configured to implement a plurality of raster operations on graphics data stored in the system memory.
대표청구항▼
1. A system for cooperative graphics processing across a graphics bus comprising: a computer system comprising: a system memory;a graphics bus;a system memory bus,a graphics processor coupled to the graphics bus; anda bridge comprising a fragment processor, the bridge being coupled to the system mem
1. A system for cooperative graphics processing across a graphics bus comprising: a computer system comprising: a system memory;a graphics bus;a system memory bus,a graphics processor coupled to the graphics bus; anda bridge comprising a fragment processor, the bridge being coupled to the system memory via the system memory bus, and to the graphics processor via the graphics bus,wherein, the graphics processor and fragment processor are configured to perform a plurality of fragment processing operations cooperatively,wherein a graphics driver executing on the computer system balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating at least a portion of the plurality of fragment processing to the fragment processor to be performed and allocating a remaining portion of the plurality of fragment processing operations to the graphics processor to be performed,further wherein, the system memory bus has a greater bandwidth than the graphics bus. 2. The system of claim 1, wherein the plurality of fragment processing operations comprises a plurality of raster operations on graphics data stored in the system memory. 3. The system of claim 1, wherein the graphics data stored in the system memory comprises a frame buffer used by the fragment processor and the graphics processor. 4. The system of claim 1, wherein the plurality of fragment processing operations comprises frame buffer blending on the graphics data in the system memory. 5. The system of claim 1, wherein the plurality of fragment processing operations comprises multi-sample expansion on graphics data received from the graphics processor and store resulting expanded data in the system memory. 6. The system of claim 1, wherein the plurality of fragment processing operations comprises evaluating a Z-plane equation coverage value for a plurality of pixels stored in the system memory, wherein the Z-plane equation coverage value is received from the graphics processor. 7. The system of claim 1, wherein the bridge is a North bridge chipset component of the computer system. 8. The system of claim 1, wherein the graphics processor is configured to use a portion of the system memory for frame buffer memory. 9. The system of claim 1, wherein the graphics processor is detachably coupled to the graphics bus by a connector. 10. The system of claim 1, wherein the graphics bus is an AGP graphics bus. 11. The system of claim 1, wherein the graphics bus is a PCI Express graphics bus. 12. The system of claim 1, wherein the graphics driver balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating as large a share as possible of the plurality of fragment processing operations to the fragment processor. 13. The system of claim 1, wherein the system memory is used as frame buffer memory for the computer system. 14. The system of claim 1, wherein an amount of data access latency experienced by performing fragment processing operations in the fragment processor is reduced relative to an amount of data access latency experienced by performing the fragment processing operations in the graphics processor. 15. A bridge for implementing cooperative graphics processing with a graphics processor coupled to the bridge across a graphics bus comprising: a computer system comprising: a system memory bus interface comprising a system memory bus;a graphics bus interface comprising a graphics bus; anda fragment processor disposed in the bridge coupled to the system memory bus, the fragment processor being configured to perform a plurality of fragment processing operations cooperatively with a graphics processor coupled to the graphics bus,wherein, a graphics driver executing on the computer system balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating at least a portion of the plurality of fragment processing operations to the fragment processor to be performed and allocating a remaining portion of the plurality of fragment processing operations to the graphics processor to be performed,further wherein, the system memory bus has a greater bandwidth than the graphics bus. 16. The bridge of claim 15, wherein the plurality of fragment processing operations comprises a plurality of raster operations on graphics data stored in the system memory. 17. The system of claim 15, wherein the bridge is configured to use a frame buffer in the system memory for the processing of graphics data. 18. The system of claim 15, wherein the plurality of fragment processing operations comprises frame buffer blending on the graphics data in the system memory. 19. The system of claim 15, wherein the plurality of fragment processing operations comprises multi-sample expansion on graphics data received from the graphics processor and store resulting expanded data in the system memory. 20. The system of claim 15 wherein the plurality of fragment processing operations comprises evaluating a Z plane equation coverage value for a plurality of pixels stored in the system memory, wherein the Z plane equation coverage value is received from the graphics processor. 21. The system of claim 15, wherein the graphics processor is detachably coupled to the graphics bus by a connector. 22. The system of claim 15, wherein the graphics driver balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating as large a share as possible of the plurality of fragment processing operations to the fragment processor. 23. The system of claim 15, wherein the system memory bus is coupled to a system memory, and wherein the system memory is used as frame buffer memory for the computer system. 24. In a bridge of a computer system, a method for cooperatively implementing fragment processing operations with a graphics processor across a graphics bus in a computer system, comprising: in a computer system, receiving at a fragment processor pre-expanded color values from the graphics processor via the graphics bus, the fragment processor, graphics processor and graphics bus being disposed in the computer system;performing a multi-sample expansion on the color values resulting in expanded color value graphics data, the multi-sample expansion comprising at least a portion of the fragment processing to be performed cooperatively by the fragment processor and the graphics processor in the computer system across the graphics bus;storing the expanded color value graphics data into a frame buffer in a system memory through a system memory bus; andrendering an image to a display, the rendering performed by the graphics processor accessing the expanded color value graphics data in the frame buffer,wherein, the multi-sample expansion is balanced by a graphics driver executing on the computer system by allocating the portion of the fragment processing to the fragment processor to be performed and allocating a remaining portion of the fragment processing to be performed cooperatively to the graphics processor to be performed,further wherein, the system memory bus has a greater bandwidth than the graphics bus. 25. The method of claim 24, further comprising: receiving Z plane equation coverage values from the graphics processor via the graphics bus;performing a Z plane iteration process to generate iterated Z values for a plurality of pixels;storing the iterated Z values into the frame buffer; andrendering the image to the display, the rendering performed by the graphics processor accessing the iterated Z values in the frame buffer. 26. The method of claim 24, wherein the bridge is a North bridge chipset component of the computer system. 27. The method of claim 26, wherein the graphics processor is detachably coupled to the graphics bus by a connector. 28. The method of claim 27, wherein the graphics bus is an AGP graphics bus. 29. The method of claim 27, wherein the graphics bus is a PCI Express graphics bus. 30. The method of claim 24, wherein the graphics driver balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating as large a share as possible of the plurality of fragment processing operations to the fragment processor. 31. The method of claim 24, wherein the system memory is used as frame buffer memory for the computer system.
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