$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

E-fuse structure design in electrical programmable redundancy for embedded memory circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/00
  • H01L-023/525
  • H01L-023/532
출원번호 US-0107917 (2013-12-16)
등록번호 US-9099467 (2015-08-04)
발명자 / 주소
  • Thei, Kong-Beng
  • Cheng, Chung Long
  • Liu, Chung-Shi
  • Chuang, Harry-Hak-Lay
  • Wu, Shien-Yang
  • Chen, Shi-Bai
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Slater & Matsil, L.L.P.
인용정보 피인용 횟수 : 1  인용 특허 : 48

초록

An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over

대표청구항

1. A method comprising: applying a voltage differential between an anode of a fuse and a cathode of the fuse, wherein a first number of conductive vias extend from the anode and are electrically coupled between the anode and the cathode, wherein a second number of conductive vias extend from the cat

이 특허에 인용된 특허 (48)

  1. Cieplik Ingeborg,DEX ; Frochte Bernd,DEX ; Rupalla Manfred,DEX, Electrical fuse.
  2. Young, Bradley Scott, Electrical fuse for semiconductor integrated circuits.
  3. Sundar K. Iyer ; Chandcasekhar Narayan ; Axel Brintzinger ; Subramanian Iyer, Electrical fuses for semiconductor devices.
  4. Srikrishnan Kris V. (Wappingers Falls NY) White James F. (Newburgh NY) Yang Jer-Ming (Changhua City TWX), Electrically blowable fuse structure manufacturing for organic insulators.
  5. Sidhu, Lakhbeer S.; Rahim, Irfan, Electrically-programmable integrated circuit fuses and sensing circuits.
  6. Chandrasekharan Kothandaraman ; Frank Grellner ; Sundar Kumar Iyer, Enhanced efuses by the local degradation of the fuse link.
  7. Yu, Ta-Lee, Fabricating an electrical metal fuse.
  8. Liu, Yauh-Ching; Castagnetti, Ruggero; Venkatraman, Ramnath, Fuse construction for integrated circuit structure having low dielectric constant dielectric material.
  9. Liu, Yauh-Ching; Castagnetti, Ruggero; Venkatraman, Ramnath, Fuse construction for integrated circuit structure having low dielectric constant dielectric material.
  10. Le, Thoai-Thai; Lindolf, Jürgen, Fuse for a semiconductor configuration and method for its production.
  11. Fukuhara Hideyuki,JPX ; Ashigaki Shigeo,JPX, Fuse in top level metal and in a step, process of making and process of trimming.
  12. Hisaka,Katushiko, Fuse layout and method trimming.
  13. Adkisson, James W.; Maciejewski, Edward; Smeys, Peter; Stamper, Anthony K., Fuse structure with thermal and crack-stop protection.
  14. Whitten Ralph G. (San Jose CA), Fusible link structure for integrated circuits.
  15. Charles R. Davis ; Daniel Charles Edelstein ; John C. Hay ; Jeffrey C. Hedrick ; Christopher Jahnes ; Vincent McGahay ; Henry A. Nye, III, Hybrid dielectric structure for improving the stiffness of back end of the line structures.
  16. Delpech Philippe,FRX ; Revil Nathalie,FRX, Integrated circuit fuse with localized fusing point.
  17. Philippe Delpech FR; Nathalie Revil FR, Integrated circuit fuse, with focusing of current.
  18. Motsiff William Thomas ; Geffken Robert Michael ; Uttecht Ronald Robert, Integrated pad and fuse structure for planar copper metallurgy.
  19. Reddy Chitranjan N. ; Medhekar Ajit K., Laser fusible link structure for semiconductor devices.
  20. Jeng Shin-Puu ; Taylor Kelly J., Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials.
  21. Sur ; Jr. Harlan Lee ; Bothra Subhas ; Lin Xi-Wei ; Manley Martin H. ; Payne Robert, Low power programmable fuse structures.
  22. Kiyokawa Tadashi,JPX, Metal film resistor having fuse function and method for producing the same.
  23. Tsai Chao-Chieh,TWX, Metal fuse in copper dual damascene.
  24. Yang, Chao-Hsiang; Chen, Charles; Lin, Wesley; Chuang, Harry; Li, Ming-Hsin; Huang, Jeng-Long, Metal fuse structure for saving layout area.
  25. Timothy Harrison Daubenspeck ; William Thomas Motsiff ; Jed Hickory Rankin, Method and structure for a semiconductor fuse.
  26. Purakh Raj Verma SG; Zia Alan Shafi SG; Yu Shan CN; Zeng Zheng SG; Manju Sarkar SG; Shao-Fu Sanford Chu SG, Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage.
  27. Rhodes, Howard E., Method for simultaneous formation of fuse and capacitor plate and resulting structure.
  28. Nakatani, Shinya; Kobayashi, Heiji, Method of fabricating a semiconductor device with a passivation film.
  29. Chuang, Harry, Method of forming a novel top-metal fuse structure.
  30. Chu-Wei Hu TW; Chung-Te Lin TW; Kuo-Hua Pan TW; Hsien-Chin Lin TW, Method of forming an aluminum protection guard structure for a copper metal structure.
  31. Stuart E. Greer, Method of forming copper interconnection utilizing aluminum capping film.
  32. Welch Michael T. (Sugarland TX) McMann Ronald E. (Rosenberg TX) Torreno ; Jr. Manuel L. (Houston TX) Garcia ; Jr. Evaristo (Rosenberg TX), Method of making a scalable fuse link element.
  33. Morrill ; Jr. Vaughan (St. Louis County MO) Scandrett John H. (St. Louis County MO) Hudson David K. (Madison County IL), Method of making a sub-miniature electrical component, particulary a fuse.
  34. Hewson, Melissa M.; Jackson, Ricky A.; Singh, Abha; Tran, Toan; Tigelaar, Howard L., Optimized metal fuse process.
  35. Huang, Yuhong, Poly fuse trim cell.
  36. Tzeng Wen-Tsing,TWX ; Chen Yue-Feng,TWX ; Wang Kau-Jan,TWX, Process for controlling oxide thickness over a fusible link using transient etch stops.
  37. Takagi Hiroshi (Hyogo JPX), Redundant circuit of semiconductor device and method of producing same.
  38. Hara Yuji (Akishima JPX) Ito Satoru (Tokyo JPX) Toya Tatsuro (Tokyo JPX), Resin molded type semiconductor device having a conductor film.
  39. Hara Yuji (Akishima JPX) Ito Satoru (Tokyo JPX) Toya Tatsuro (Tokyo JPX), Resin molded type semiconductor device having a conductor film.
  40. Hara Yuji (Akishima JPX) Ito Satoru (Tokyo JPX) Toya Tatsuro (Tokyo JPX), Resin molded type semiconductor device having a conductor film.
  41. Welch Michael T. (Sugarland TX) McMann Ronald E. (Rosenberg TX) Torreno ; Jr. Manuel L. (Houston TX) Garcia ; Jr. Evaristo (Rosenberg TX), Scalable fuse link element.
  42. Takase,Shunji, Semiconductor device.
  43. Hashimoto, Shingo, Semiconductor device having a fuse and a low heat conductive section for blowout of fuse.
  44. Hideto Hidaka JP; Mikio Asakura JP; Kiyohiro Furutani JP; Tetsuo Kato JP, Semiconductor memory device and method of checking same for defect.
  45. Boku Katsushi (Tsuchiura JPX), Sidewall formation process for a top lead fuse.
  46. Bohr Mark T. ; Alavi Mohsen, Silicide agglomeration fuse device.
  47. Ta-Lee Yu TW, Silicide agglomeration poly fuse device.
  48. Yu, Ta Lee, Silicide agglomeration poly fuse device.

이 특허를 인용한 특허 (1)

  1. Cao, Qing; Cheng, Kangguo; Li, Zhengwen; Liu, Fei, Dielectric thermal conductor for passivating efuse and metal resistor.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로