초록 ▼

Through substrate via (TSuV) structures and method of making the same are disclosed herein. In embodiments, TSuV structures are metal filled selectively to avoid forming significant metal overburden on non-via surfaces of the substrate. In certain embodiments, post-fill metal removal/planarization o

Through substrate via (TSuV) structures and method of making the same are disclosed herein. In embodiments, TSuV structures are metal filled selectively to avoid forming significant metal overburden on non-via surfaces of the substrate. In certain embodiments, post-fill metal removal/planarization operations are eliminated for reduced process complexity and manufacturing cost. In embodiments, selective metal fill entails selective electroless or electrolytic deposition. Both front side and back side selective deposition methods are described along with features of through substrate via structures made with such methods.

대표청구항 ▼

1. A microelectronic device, comprising: a substrate including a first surface and a second surface;a through substrate via (TSuV) extending through the substrate between the first surface and the second surface;a dielectric liner in contact with the substrate;a catalytic material in contact with th

1. A microelectronic device, comprising: a substrate including a first surface and a second surface;a through substrate via (TSuV) extending through the substrate between the first surface and the second surface;a dielectric liner in contact with the substrate;a catalytic material in contact with the dielectric liner at an inside sidewall surface of the TSuV, the inside sidewall surface extending from the first surface to the second surface, wherein the catalytic material extends along the inside sidewall surface only partially between the first surface and the second surface; anda metal disposed within the TSuV, wherein the metal is in direct contact with the catalytic material. 2. The microelectronic device of claim 1, wherein the catalytic material is a metal film or a layer of metal particles comprising at least one of: palladium (Pd), silver (Ag), gold (Au), iridium (Ir), osmium (Os), platinum (Pt), rhodium (Rh), ruthenium (Ru), nickel (Ni), cobalt (Co), iron (Fe), tin (Sn), bismuth (Bi), cadmium (Cd), titanium (Ti), tantalum (Ta), vanadium (V), tungsten (W), aluminum (Al), or copper (Cu). 3. The microelectronic device of claim 1, wherein the catalytic material is a photosensitive film comprising at least one of: titanium oxide (TiO2), tin oxide (SnO2), zinc oxide (ZnO), and lead iodide (PbI2), and wherein the photosensitive film has catalytic particles comprising at least one of: palladium (Pd), platinum (Pt), silver (Ag), gold (Au), nickel (Ni), cobalt (Co), or copper (Cu). 4. The microelectronic device of claim 1, wherein the dielectric liner comprises at least one of: silicon dioxide (SiO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), silicon nitride (SixNy), silicon carbide (SiC), silicon oxy-carbo-nitride (SiOCN), a benzocyclobutene (BCB)-based polymer, or a (p-xylylene)-based polymer. 5. The microelectronic device of claim 4, wherein the dielectric liner has the catalytic material on the liner surface and wherein the metal is in direct contact with the dielectric liner. 6. The microelectronic device of claim 5, wherein the dielectric liner comprises at least one of silicon nitride, silicon carbide, silicon oxy-carbo-nitride, or a (p-xylylene)-based polymer. 7. The microelectronic device of claim 1, wherein the metal comprises Cu and at least 1 PPM of at least one of: hydrogen (H), chlorine (Cl), oxygen (O), sulfur (S), carbon (C), or nitrogen (N). 8. The microelectronic device of claim 1, wherein the metal further comprises a diffusion barrier layer disposed over the dielectric liner, the diffusion barrier layer comprising at least one of nickel (Ni) or cobalt (Co) alloyed with at least one of: boron (B), phosphorus (P), nitrogen (N), tungsten (W), molybdenum (Mo), or rhenium (Re). 9. The microelectronic device of claim 1, wherein the TSuV extends between a bump disposed over a dielectric layer disposed over a front side of the substrate to a second bump disposed over a back side of the substrate. 10. The microelectronic device of claim 1, wherein the substrate has bumps on both a front side and a back side, and wherein the device further comprises a front side metal pad disposed over a front side of the substrate with a dielectric layer disposed between the front side bump and the front side metal pad, and wherein the TSuV extends between the front side metal pad and a back side bump. 11. The microelectronic device of claim 1, wherein the substrate has bumps on both a front side and a back side, and wherein the device further comprises a front side metal pad disposed over a front side of the substrate with at least one interconnect layer disposed between the front side bump and front side metal pad, and wherein the device further comprises a backside redistribution layer having at least one metal layer, and wherein the TSuV extends between the front side pad and metal of the redistribution layer. 12. A microelectronic device assembly comprising: a first of the microelectronic device in claim 1, wherein at least one first metal bump is disposed on a surface of a first TSuV; anda second of the microelectronic device in claim 1, wherein at least one second metal bump is disposed on a surface of a second TSuV, and wherein the first and second TSuVs are stacked together with the first and second metal bumps bonded together. 13. A microelectronic device assembly comprising: a first of the microelectronic device in claim 1 comprising a first TSuV; anda second of the microelectronic device in claim 1 comprising a second TSuV, wherein a first metal bump is disposed on a surface of the first TSuV, and wherein the first and second TSuVs are stacked together with the first metal bump bonded directly to the second TSuV. 14. The microelectronic device assembly of claim 13, wherein the second TSuV is partially filled, with the via metal recessed from a surface of the substrate and the first metal bump disposed in the recess. 15. The microelectronic device assembly of claim 14, wherein the via metal partially filling the second TSuV comprises a surface finish metal distinct from the metal of the first metal bump.