3D semiconductor device and structure with back-bias
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-025/00
H01L-025/065
H01L-021/683
H01L-021/74
H01L-021/762
H01L-021/768
H01L-021/822
H01L-021/8238
H01L-021/84
H01L-023/48
H01L-023/525
H01L-027/02
H01L-027/06
H01L-027/092
H01L-027/10
H01L-027/105
H01L-027/108
H01L-027/11
H01L-027/112
H01L-027/115
H01L-027/118
H01L-027/12
H01L-029/423
H01L-029/66
H01L-029/78
H01L-029/788
H01L-029/792
H01L-023/367
H01L-023/00
출원번호
US-0492395
(2012-06-08)
등록번호
US-9136153
(2015-09-15)
발명자
/ 주소
Or-Bach, Zvi
Sekar, Deepak C.
Cronquist, Brian
Beinglass, Israel
Wurman, Ze'ev
Lim, Paul
출원인 / 주소
MONOLITHIC 3D INC.
대리인 / 주소
Tran & Associates
인용정보
피인용 횟수 :
15인용 특허 :
337
초록▼
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.
대표청구항▼
1. A 3D semiconductor device, comprising: a first layer comprising first transistors;a first interconnection layer interconnecting said first transistors and comprises aluminum or copper;a second layer comprising second transistors; andat least one through-layer via; wherein said at least one throug
1. A 3D semiconductor device, comprising: a first layer comprising first transistors;a first interconnection layer interconnecting said first transistors and comprises aluminum or copper;a second layer comprising second transistors; andat least one through-layer via; wherein said at least one through-layer via comprises a conductive path through said second layer,wherein said at least one through-layer via has a diameter less than 200 nm,wherein said second layer comprises at least one Flip-Flop,wherein said second layer is overlying said first interconnection layer, andwherein at least one of said second transistors has a back-bias structure designed to modify the performance of said at least one of said second transistors, wherein said second transistors comprise mono-crystalline material. 2. A 3D semiconductor device according to claim 1, wherein the interconnection layer is between said first layer and said second layer;wherein said second transistors are horizontally oriented transistors. 3. A 3D semiconductor device according to claim 1, wherein said second transistors comprise a source contact, said source contact comprising a silicide, andwherein said silicide has a sheet resistance of less than 15 ohm/sq. 4. A 3D semiconductor device according to claim 1, wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors. 5. A 3D semiconductor device according to claim 1, wherein the interconnection layer is between said first layer and said second layer;wherein said second transistors comprise mono-crystalline material,wherein said second transistors are horizontally oriented transistors, andwherein said second transistors are Fin-FET transistors. 6. A 3D semiconductor device according to claim 1, wherein said second transistors are fully depleted transistors. 7. A 3D semiconductor device according to claim 1, further comprising: a heat spreader layer disposed between said first layer and said second layer. 8. A 3D semiconductor device, comprising: a first layer comprising first transistors;a first interconnection layer interconnecting said first transistors and comprises aluminum or copper;a second layer comprising second transistors; andat least one through-layer via; wherein said at least one through-layer via comprises a conductive path through said second layer,wherein said at least one through-layer via has a diameter less than 200 nm,wherein said second layer is overlying said first interconnection layer,wherein at least one of said second transistors has a back-bias structure, wherein said second transistors comprise mono-crystalline material. 9. A 3D semiconductor device according to claim 8, wherein the interconnection layer is between said first layer and said second layer;wherein said second transistors are horizontally oriented transistors. 10. A 3D semiconductor device according to claim 8, wherein said second transistors comprise a source contact, said source contact comprising a silicide, andwherein said silicide has a sheet resistance of less than 15 ohm/sq. 11. A 3D semiconductor device according to claim 8, wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors. 12. A 3D semiconductor device according to claim 8, further comprising: a heat spreader layer disposed between said second layer and said interconnection layer, wherein the interconnection layer is between said first layer and said second layer. 13. A 3D semiconductor device according to claim 8, wherein said second transistors are fully depleted transistors. 14. A 3D semiconductor device according to claim 8, wherein at least two of said second transistors have a common shared diffusion. 15. A 3D semiconductor device, comprising: a first layer comprising first transistors;a second layer comprising second transistors; wherein said second layer is overlying said first transistors,wherein said second transistors comprise a first mono-crystalline material,wherein at least one of said second transistors has a back-bias structure,at least one through-layer via; wherein said at least one through-layer via comprises a conductive path through said second layer,wherein said at least one through-layer via has a diameter less than 200 nm, andan interconnection layer between said first layer and said second layer, wherein said interconnection layer comprises copper or aluminum,wherein said second layer comprises a plurality of Flip-Flops, andwherein said plurality of Flip-Flops comprise scanned Flip-Flops connected with a scan chain. 16. A 3D semiconductor device according to claim 15, wherein said second transistors are horizontally oriented transistors. 17. A 3D semiconductor device according to claim 15, wherein said second transistors comprise a source contact, said source contact comprising a silicide, andwherein said silicide has a sheet resistance of less than 15 ohm/sq. 18. A 3D semiconductor device according to claim 15, wherein said first transistors are down-looking transistors and said second transistors are up-looking transistors. 19. A 3D semiconductor device according to claim 15, wherein said second transistors are fully depleted transistors. 20. A 3D semiconductor device according to claim 15, further comprising: a heat spreader layer disposed between said first layer and said second layer.
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