Field effect transistor devices with low source resistance
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/78
H01L-029/06
H01L-029/739
H01L-029/04
H01L-029/16
출원번호
US-0108440
(2011-05-16)
등록번호
US-9142662
(2015-09-22)
발명자
/ 주소
Ryu, Sei-Hyung
Capell, Doyle Craig
Cheng, Lin
Dhar, Sarit
Jonas, Charlotte
Agarwal, Anant
Palmour, John
출원인 / 주소
Cree, Inc.
대리인 / 주소
Myers Bigel Sibley & Sajovec, P.A.
인용정보
피인용 횟수 :
4인용 특허 :
162
초록▼
A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel reg
A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
대표청구항▼
1. A semiconductor device comprising: a channel region extending in a first direction;a lateral source region adjacent and parallel to the channel region;a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact re
1. A semiconductor device comprising: a channel region extending in a first direction;a lateral source region adjacent and parallel to the channel region;a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; anda source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions; wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; andwherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V. 2. The semiconductor device of claim 1, wherein a minimum dimension of an area of contact of the source ohmic contact on the plurality of source contact regions is such that the semiconductor device has a reverse blocking voltage of 1000 volts or more and the device is capable of a forward current greater than 100 A at a forward voltage of 5 volts or less. 3. The semiconductor device of claim 1, wherein the semiconductor device comprises a metal-oxide semiconductor field effect transistor device having a reverse blocking voltage of 1200 volts or more. 4. The semiconductor device of claim 1, wherein a minimum dimension of an area of the source ohmic contact on the plurality of source contact regions is arranged in the layout such that the semiconductor device has a blocking voltage less than 1000 V and is configured to pass forward current at a current density greater than 200 amps per square centimeter at a forward voltage drop of 5 V or less. 5. The semiconductor device of claim 1, wherein the plurality of source contact regions is arranged in the layout with the source ohmic contact and the first and second contact regions such that a ratio of sheet resistance in ohms per square of the plurality of source contact regions to contact resistance in ohms per square area is greater than 1, wherein the square is equal in size to the square area. 6. The semiconductor device of claim 1, wherein the plurality of source contact regions is arranged in the layout with the source ohmic contact and the first and second contact regions to have a sheet resistance in ohms per square greater than 75% of a contact resistance hi ohms per square area such that the semiconductor device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter at a current greater than 100 A, wherein the square is equal in size to the square area. 7. The semiconductor device of claim 1, wherein the plurality of source contact regions is arranged in the layout with the source ohmic contact and the first and second contact regions such that a sheet resistance in ohms per square of the plurality of source contact regions is greater than a contact resistance in ohms per square area of the plurality of source contact regions, wherein the square is equal in size to the square area. 8. The semiconductor device of claim 1, wherein the plurality of source contact regions is arranged in the layout with the source ohmic contact and the first and second contact regions such that a sheet resistance in ohms per square of the plurality of source contact regions is at least 5 times greater than a contact resistance in ohms per square area of the plurality of source contact regions, wherein the square is equal in size to the square area. 9. The semiconductor device of claim 1, wherein the plurality of source contact regions has a sheet resistance and the source ohmic contact has a contact resistance, wherein the contact resistance in ohms per square area is greater than the sheet resistance in ohms per area, wherein the square is equal in size to the square area. 10. The semiconductor device of claim 1, further comprising a source region including the lateral source region and the source contact regions, wherein the source region is arranged in the layout to surround the first and second body contact regions. 11. The semiconductor device of claim 10, wherein the source region is arranged in the layout to surround the first and second body contact regions at a same level as the plurality of contact regions. 12. The semiconductor device of claim 1, wherein a cell pitch of the semiconductor device is less than 10 μm. 13. The semiconductor device of claim 1, wherein the layout comprises a number of source contact regions contacting the source ohmic contact that is one greater than a number of contact regions contacting the source ohmic contact. 14. The semiconductor device of claim 1, wherein the number of source contact regions contacting the source ohmic contact is three and the number of contact regions contacting the source ohmic contact is two. 15. The semiconductor device of claim 1, wherein a minimum dimension of an area of contact between the source ohmic contact on the plurality of source contact regions is arranged in the layout such that the semiconductor device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter at a current greater than 100 A. 16. The semiconductor device of claim 1, wherein the plurality of contact regions are arranged in the layout with the plurality of source contact regions such that the first and second body contact regions are not physically contacting each other. 17. The semiconductor device of claim 1, wherein a minimum dimension of an area of the source ohmic contact on the plurality of source contact regions is arranged in a layout such that the semiconductor device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter at a current greater than 100 A. 18. A semiconductor device comprising: a channel region extending in a first direction;a lateral source region adjacent and parallel to the channel region;a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; anda source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions; wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; andwherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V. 19. A semiconductor device comprising: a channel region extending in a first direction;a lateral source region adjacent and parallel to the channel region;a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; anda source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions; wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; andwherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V. 20. The insulated gate bipolar transistor device of claim 19, wherein a minimum dimension of an area of the source ohmic contact on the plurality of source contact regions is arranged in the layout such that the insulated gate bipolar transistor device has a blocking voltage of 13 kV or more and the insulated gate bipolar transistor device is capable of a forward current of 5 A or greater. 21. The insulated gate bipolar transistor device of claim 19, wherein the insulated gate bipolar transistor device has a specific on-resistance of less than 14 mOhm-cm2. 22. The insulated gate bipolar transistor device of claim 21, wherein the insulated gate bipolar transistor device has a voltage blocking capability of 10 kV or more. 23. A semiconductor device comprising: a channel region extending in a first direction;a lateral source region adjacent and parallel to the channel region;a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; anda source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions; wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; andwherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V. 24. The metal-oxide semiconductor field effect transistor device of claim 23, wherein the cell pitch is less than 10 μm. 25. A semiconductor device comprising: a channel region extending in a first direction;a lateral source region adjacent and parallel to the channel region;a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; anda source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions; wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; andwherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (162)
Smith, Richard Peter, Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment.
Edmond John A. (Apex NC) Dmitriev Vladimir (Fuquay-Varina NC) Irvine Kenneth (Cary NC), Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices.
Gardner Mark I. ; Hause Fred N. ; Fulford ; Jr. H. Jim, CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMO.
Bakowski Mietek,SEX ; Gustafsson Ulf,SEX ; Rottner Kurt,SEX ; Savage Susan,SEX, Fabrication of a SiC semiconductor device comprising a pn junction with a voltage absorbing edge.
Brown Dale M. (Schenectady NY) Michon Gerald J. (Waterford NY) Krishnamurthy Vikram B. (Latham NY) Kretchmer James W. (Ballston Spa NY), Fabrication of silicon carbide integrated circuits.
Khan Muhammed A. (White Bear Lake) VanHove James M. (Eagan) Kuznia Jon N. (Fridley) Olson Donald T. (Circle Pines MN), High electron mobility transistor with GaN/AlxGa1-xN heterojunctions.
Miyata Koichi (Kobe JPX) Saito Kimitsugu (Kobe NC JPX) Dreifus David L. (Cary NC) Stoner Brian R. (Raleigh NC), Highly oriented diamond film field-effect transistor.
Kong Hua-Shuang (Raleigh NC) Glass Jeffrey T. (Apex NC) Davis Robert F. (Raleigh NC), Homoepitaxial growth of Alpha-SiC thin films and semiconductor devices fabricated thereon.
Moise Theodore S. ; Xing Guoqiang ; Visokay Mark ; Gaynor Justin F. ; Gilbert Stephen R. ; Celii Francis ; Summerfelt Scott R. ; Colombo Luigi, Integrated circuit and method.
Smrtic Mark A. (Stoneham MA) Molnar George M. (Flemington NJ) Lapham Jerome F. (Groton MA), Integrated circuit metal-oxide-metal capacitor and method of making same.
Shah,Pankaj B., Interacting current spreader and junction extender to increase the voltage blocked in the off state of a high power semiconductor device.
Smayling Michael C. (Missouri City TX) Torreno ; Jr. deceased Manuel J. (late of Houston TX by Arlene Torreno ; executrix) Falessi George (Villeneuve-Loubet FRX), LDMOS transistor with self-aligned source/backgate and photo-aligned gate.
Williams Richard K. ; Darwish Mohamed ; Grabowski Wayne ; Cornell Michael E., Low resistance power MOSFET or other device containing silicon-germanium layer.
Harris Christopher,SEX ; Konstantinov Andrei,SEX ; Janzen Erik,SEX, Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of highly d.
Tsui Paul G. Y. ; Tseng Hsing-Huang ; Bhat Navakanta ; Chen Ping, Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region.
Ghezzo Mario (Ballston Lake NY) Chow Tat-Sing P. (Schenectady NY) Kretchmer James W. (Ballston Spa NY) Saia Richard J. (Schenectady NY) Hennessy William A. (Niskayuna NY), Method of fabricating a self-aligned DMOS transistor device using SiC and spacers.
Singh Ranbir ; Agarwal Anant K. ; Ryu Sei-Hyung, Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices.
Paul Chang ; Geeng-Chuan Chern ; Wayne Y. W. Hsueh ; Vladimir Rodov, Method of fabricating power rectifier device to vary operating parameters and resulting device.
Kong Hua-Shuang (Raleigh NC) Carter ; Jr. Calvin H. (Cary NC), Method of improving mechanically prepared substrate surfaces of alpha silicon carbide for deposition of beta silicon car.
Khan Muhammad A. (White Bear Lake MN) VanHove James M. (Eagan MN) Kuznia Jon N. (Fridley MN) Olson Donald T. (Circle Pines MN), Method of making a high electron mobility transistor.
Kumar Rajesh,JPX ; Naito Masami,JPX ; Nakamura Hiroki,JPX ; Takeuchi Yuichi,JPX, Method of manufacturing silicon carbide semiconductor device using active and inactive ion species.
Sei-Hyung Ryu ; Joseph J. Sumakeris ; Anant K. Agarwal ; Ranbir Singh, Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation.
Korman Charles S. (Schenectady NY) Baliga Bantval J. (Raleigh NC) Chang Hsueh-Rong (Scotia NY), Multicellular FET having a Schottky diode merged therewith.
Anderson Wayne A. (Hamburg NY) Jia Quanxi (Los Alamos NM) Yi Junsin (Amherst NY) Chang Lin-Huang (Tonawanda NY), Nanocrystalline layer thin film capacitors.
Agarwal Anant K. (Monroeville PA) Siergiej Richard R. (Irwin PA) Brandt Charles D. (Mt. Lebanon PA) White Marvin H. (Bethlehem PA), Non-volatile random access memory cell constructed of silicon carbide.
Narwankar Pravin K. ; Sahin Turgut ; Redinbo Gregory F. ; Liu Patricia M. ; Tran Huyen T., Post deposition treatment of dielectric films for interface control.
Rodov, Vladimir; Chang, Paul; Bao, Jianren; Hsueh, Wayne Y. W.; Chiang, Arthur Ching-Lang; Chern, Geeng-Chuan, Power diode having improved on resistance and breakdown voltage.
Chong-man Yun KR; Tae-hoon Kim KR; Ho-cheol Jang KR; Young-chull Choi KR, Power semiconductor device having low on-resistance and high breakdown voltage.
Ryu, Sei-Hyung; Agarwal, Anant; Das, Mrinal Kanti; Lipkin, Lori A.; Palmour, John W.; Singh, Ranbir, SILICON CARBIDE POWER METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING A SHORTING CHANNEL AND METHODS OF FABRICATING SILICON CARBIDE METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING.
Suvorov Alexander ; Palmour John W. ; Singh Ranbir, Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion.
Ghezzo Mario ; Chow Tat-Sing Paul ; Kretchmer James William ; Saia Richard Joseph ; Hennessy William Andrew, Self-aligned transistor device including a patterned refracting dielectric layer.
Friedrichs, Peter; Peters, Dethard; Schoerner, Reinhold, Semiconductor device made from silicon carbide with a Schottky contact and an ohmic contact made from a nickel-aluminum material.
Harris Christopher,SEX ; Bijlenga Bo,SEX ; Zdansky Lennart,SEX ; Gustafsson Ulf,SEX ; Bakowski Mietek,SEX ; Konstantinov Andrey,SEX, Semiconductor device of SiC having an insulated gate and buried grid region for high breakdown voltage.
Schorner Reinhold,DEX ; Stephani Dietrich,DEX ; Peters Dethard,DEX ; Friedrichs Peter,DEX, Semiconductor structure having a predetermined alpha-silicon carbide region, and use of this semiconductor structure.
Bakowsky Mietek,SEX ; Bijlenga Bo,SEX ; Gustafsson Ulf,SEX ; Harris Christopher,SEX ; Savage Susan,SEX, SiC Semiconductor device comprising a pn Junction with a voltage absorbing edge.
Shah, Pankaj B., Silicon carbide (SiC) gate turn-off (GTO) thyristor structure for higher turn-off gain and larger voltage blocking when in the off-state.
Ryu, Sei-Hyung, Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same.
Kumar,Rajesh; Mihaila,Andrei; Udrea,Florin, Silicon carbide semiconductor device having junction field effect transistor and method for manufacturing the same.
Davis Robert F. (Raleigh NC) Carter ; Jr. Calvin H. (Raleigh NC) Hunter Charles E. (Durham NC), Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide.
Peake, Steven T.; Petkos, Georgios; Farr, Robert J.; Rogers, Christopher M.; Grover, Raymond J.; Forbes, Peter J., Trench-gate semiconductor devices and their manufacture.
Degenhardt Charles R. (The Procter & Gamble Company ; Miami Valley Laboratories ; P.O. Box 398707 Cincinnati OH 45239-8707) Kozikowski Barbara A. (The Procter & Gamble Company ; Miami Valley Laborato, Use of a carboxy-substituted polymer to inhibit plaque formation without tooth staining.
Edmond John A. (Cary NC) Bulman Gary E. (Cary NC) Kong Hua-Shuang (Raleigh NC) Dmitriev Vladimir (Fuquay-Varina NC), Vertical geometry light emitting diode with group III nitride active layer and extended lifetime.
Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant Kumar; Palmour, John Williams; Allen, Scott, Power module for supporting high current densities.
Henning, Jason Patrick; Zhang, Qingchun; Ryu, Sei-Hyung; Agarwal, Anant Kumar; Palmour, John Williams; Allen, Scott, Power module having a switch module for supporting high current densities.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.