IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0537297
(2012-06-29)
|
등록번호 |
US-9158500
(2015-10-13)
|
우선권정보 |
KR-10-2011-0065195 (2011-06-30) |
발명자
/ 주소 |
- Lee, Ki Jun
- Kong, Jun Jin
- Kim, Yong June
- Kim, Jae Hong
- Son, Hong Rak
- Chung, Jung Soo
- Choi, Seong Hyeong
|
출원인 / 주소 |
- Samsung Electronics Co., Ltd.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
0 인용 특허 :
8 |
초록
▼
A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift regist
A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.
대표청구항
▼
1. A data processing device comprising: a single pseudo random number generator including a series connection of plural shift registers;a polynomial coefficient controller configured to generate a memory parameter MP referring to data stored in a table and transmit the memory parameter MP for determ
1. A data processing device comprising: a single pseudo random number generator including a series connection of plural shift registers;a polynomial coefficient controller configured to generate a memory parameter MP referring to data stored in a table and transmit the memory parameter MP for determining a feedback polynomial of the single pseudo random number generator to the single pseudo random number generator;a selector configured to receive an output from each of the plural shift registers, and to select an output from one of the plural shift registers excluding a last shift register of the series connection as a pseudo random number sequence; anda conversion circuit which receives the pseudo random number sequence from the selector, and which converts first data to second data using the received pseudo random number sequence,wherein the selector is configured to select the output from the one of the plural shift registers responsive to the memory parameter MP, and wherein the memory parameter MP comprises a memory access parameter of the first or second data, andwherein the memory parameter MP is configured for accessing a flash memory including a block including a plurality of pages, and wherein the memory access parameter is at least one of a block address, a page address, a word line address, a bit line address, a chip identification (ID) of the flash memory, a program count and an erase count. 2. The device of claim 1, wherein the single pseudo random number generator comprises a feedback polynomial determination circuit which determines the feedback polynomial of the single pseudo random number generator in accordance with the memory parameter MP. 3. The device of claim 2, wherein the conversion includes randomizing the first data to obtain the second data which is randomized, and the conversion circuit is configured to execute a modulo addition operation on the first data and the pseudo random number sequence. 4. The device of claim 2, wherein the conversion includes de-randomizing the first data to obtain the second data which is de-randomized, and the conversion circuit is configured to execute a modulo subtraction operation on the first data and the pseudo random number sequence. 5. The device of claim 2, wherein the memory access parameter is a word line address or a bit line address. 6. The device of claim 2, wherein the single pseudo random number generator is one of a Fibonacci linear feedback pseudo random number generator, a Galois linear feedback pseudo random number generator, a Fibonacci non-linear feedback pseudo random number generator and a Galois non-linear feedback pseudo random number generator. 7. The device of claim 1, wherein the single pseudo random number generator comprises a logic gate array including a plurality of Boolean logic gates and determines a logic output corresponding to the pseudo random number sequence in accordance with the memory parameter MP. 8. A data processing device comprising: a single pseudo random number generator including a series connection of plural shift registers;a polynomial coefficient controller configured to generate a memory parameter MP referring to data stored in a table and transmit the memory parameter MP for determining a feedback polynomial of the single pseudo random number generator to the single pseudo random number generator;a selector configured to receive an output from each of the plural shift registers, and to select an output from one of the plural shift registers excluding a last shift register of the series connection as a pseudo random number sequence;a combination circuit configured to connect at least two output terminals of at least two shift registers among the plural shift registers connected in series, to combine output signals of the at least two shift registers and to generate a pseudo random number sequence; anda conversion circuit connected to the combination circuit, which receives the pseudo random number sequence output from the combination circuit, and which converts first data to second data using the received pseudo random number sequence,wherein the selector is configured to select the output from the one of the plural shift registers responsive to the memory parameter MP, and wherein the memory parameter MP comprises a memory access parameter of the first or second data, andwherein the memory parameter MP is configured for accessing a flash memory including a block including a plurality of pages, and wherein the memory access parameter is at least one of a block address, a page address, a word line address, a bit line address, a chip identification (ID) of the flash memory, a program count and an erase count. 9. The device of claim 8, wherein the single pseudo random number generator comprises a feedback polynomial determination circuit which determines a feedback polynomial of the pseudo random number generator in accordance with the memory access parameter of the first or second data. 10. The device of claim 9, wherein the conversion includes randomizing the first data to obtain the second data which is randomized, and the conversion circuit is configured to execute a modulo addition operation on the first data and the pseudo random number sequence. 11. The device of claim 9, wherein the conversion includes de-randomizing the first data to obtain the second data which is de-randomized, and the conversion circuit is configured to execute a modulo subtraction operation on the first data and the pseudo random number sequence. 12. The device of claim 9, wherein the memory access parameter is a word line address or a bit line address. 13. The device of claim 8, wherein the pseudo random number generator comprises a logic gate array including a plurality of Boolean logic gates and determines a logic output corresponding to the pseudo random number sequence in accordance with the memory access parameter of the first or second data. 14. The device of claim 8, wherein the combination circuit selectively combines output signals of the at least two shift registers among the plural shift registers in accordance with the memory access parameter of the first or second data. 15. The device of claim 8, wherein the combination circuit is configured to selectively execute at least one of first and second operations for combining the output signals of the at least two shift registers in accordance with the memory access parameter of the first or second data, wherein the first and second operations are modulo-P addition and modulo-P multiplication, respectively, where P is a natural number of more than 2. 16. A method for operating a data processing device, the method comprising: providing a single pseudo random number generator including a series connection of plural shift registers;generating a memory parameter MP referring to data stored in a table;transmitting the memory parameter MP for determining a feedback polynomial of the single pseudo random number generator to the single pseudo random number generator;generating a pseudo random number sequence using the series connection of the plural shift registers,said generating comprising selecting an output from one of the plural shift registers excluding a last shift register of the series connection as the pseudo random number sequence; andconverting first data to second data using the pseudo random number sequence,wherein said selecting is responsive to the memory parameter MP and wherein the memory parameter MP corresponds to the first or second data,wherein the memory parameter MP comprises a memory access parameter of the first or second data, andwherein the memory parameter MP is configured for accessing a flash memory including a block including a plurality of pages, and wherein the memory access parameter is at least one of a block address, a page address, a word line address, a bit line address, a chip identification (ID) of the flash memory, a program count and an erase count. 17. The method of claim 16, further comprising determining a feedback polynomial of the single pseudo random number generator in accordance with the memory parameter MP. 18. The method of claim 17, wherein the converting includes randomizing the first data to obtain the second data which is randomized. 19. The method of claim 17, wherein the converting includes de-randomizing the first data to obtain the second data which is de-randomized. 20. A data processing device comprising: a memory;a single pseudo random number generator including a series connection of plural shift registers;a polynomial coefficient controller configured to generate a memory parameter MP referring to data stored in a table and transmit the memory parameter MP for determining a feedback polynomial of the single pseudo random number generator to the single pseudo random number generator;a selector configured to receive an output from each of the plural shift registers, and to select an output from one of the plural shift registers excluding a last shift register of the series connection as a pseudo random number sequence;a randomizer which randomizes first data to obtain random second data for storage in the memory, the randomizer randomizing the first data using the pseudo random number sequence; anda de-randomizer which de-randomizes third data read from the memory to obtain de-randomized fourth data using the pseudo random number sequence,wherein the selector is configured to select the output from the one of the plural shift registers responsive to the memory parameter MP, and wherein the memory parameter MP comprises a memory access parameter of the second or third data, andwherein the memory parameter MP is configured for accessing a flash memory including a block including a plurality of pages, and wherein the memory access parameter is at least one of a block address, a page address, a word line address, a bit line address, a chip identification (ID) of the flash memory, a program count and an erase count. 21. The device of claim 20, wherein the single pseudo random number generator comprises a feedback polynomial determination circuit determining the feedback polynomial in accordance with the memory parameter MP, and wherein the memory parameter MP comprises respective memory access parameters of the second and third data.
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