|국가/구분||United States(US) Patent 등록|
|국제특허분류(IPC7판)||G06F-015/00 G06F-015/76 G06F-015/78 G06F-013/40|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 0 인용 특허 : 437|
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfigura...
1. An adaptive computing engine comprising: a first configurable computational unit including a first plurality of heterogeneous computational elements, the first plurality of heterogeneous computational elements including an adder, a register, and a function generator, the first plurality of heterogeneous computational elements coupled to each other via a first interconnection network to configure interconnections between the computational elements in response to configuration information to perform a first function;a second configurable computational u...