Hot carrier generation and programming in NAND flash
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G11C-016/00
G11C-016/34
출원번호
US-0940010
(2013-07-11)
등록번호
US-9171636
(2015-10-27)
발명자
/ 주소
Chang, Kuo-Pin
Yeh, Wen-Wei
Chang, Chih-Shen
Lue, Hang-Ting
출원인 / 주소
Macronix International Co. Ltd.
대리인 / 주소
Suzue, Kenta
인용정보
피인용 횟수 :
0인용 특허 :
15
초록▼
A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The contr
A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.
대표청구항▼
1. A memory comprising: a three-dimensional array of memory cells having a plurality of levels of memory cells;a plurality of word lines, and a plurality of bit lines; andcontrol circuitry coupled to the plurality of word lines and the plurality of bit lines, adapted for programming a selected memor
1. A memory comprising: a three-dimensional array of memory cells having a plurality of levels of memory cells;a plurality of word lines, and a plurality of bit lines; andcontrol circuitry coupled to the plurality of word lines and the plurality of bit lines, adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting, wherein the control circuitry during a program interval further performs: applying a program disturb relief voltage to a program disturb relief word line to reduce program disturb during at least part of the program interval, another word line in between the selected word line and the program disturb relief word line, the program disturb relief voltage being less than drain-side pass voltages and source-side pass voltages, andwherein the array includes semiconductor strips on which memory cells are arranged in series, and including programming the selected memory cell during the program interval by: biasing one of a first end and a second end of the series of the memory cells in the series to a drain side voltage, and another of the first end and the second end to a source side voltage during the program interval,applying the drain-side pass voltages to a first subset of the plurality of word lines between the selected word line and said one of the first end and the second end during the program interval,applying the source-side pass voltages to a second subset of the plurality of word lines between the selected word line and said other of the first end and the second end during the program interval,applying a program voltage to the selected word line during the program interval; andapplying a switching voltage to the switching word line of the plurality of word lines and to a corresponding memory cell of the memory cells in the series to control hot-carrier programming during at least part of the program interval, the switching word line being the another word line adjacent to the selected word line, and the corresponding memory cell adjacent to the selected memory cell. 2. The memory of claim 1, wherein the memory cells comprise floating body, dual gate memory cells. 3. The memory of claim 1, wherein the array comprises a plurality of stacks of semiconductor strips coupled via switches to contact pads, vertical word lines between the stacks with memory cells at cross points between the vertical word lines and the semiconductor strips, and the plurality of bit lines coupled to the contact pads. 4. The memory of claim 1, wherein the program interval includes a first program stage and a second program stage. 5. The memory of claim 4, wherein during the first stage the selected memory cell undergoes at least hot-carrier generation, and during the second stage the selected memory cell undergoes at least Fowler-Nordheim carrier injection. 6. The memory of claim 1, wherein the switching voltage is a first switching voltage during the first program stage and a second switching voltage during the second program stage, and the first switching voltage and the second switching voltage have opposite polarities. 7. The memory of claim 1, wherein the control circuitry applies the program disturb relief voltage to the program disturb relief word line of the plurality of word lines and to another corresponding memory cell of the memory cells in the series to reduce program disturb during at least part of the program interval, said another corresponding memory cell adjacent to the corresponding memory cell. 8. The memory of claim 1, wherein the program voltage is equal to the drain-side pass voltages and the source-side pass voltages. 9. The memory of claim 1, wherein during the program interval, the selected memory cell undergoes source-side boosting of hot-carrier programming of the selected memory cell. 10. The memory of claim 1, wherein during the program interval, the selected memory cell undergoes drain-side boosting of hot-carrier programming of the selected memory cell. 11. The memory of claim 1, further comprising: a first select line controlling a first access transistor coupled to the first end of the series, the first end coupled to a source line; anda second select line controlling a second access transistor coupled to the second end of the series, the second end coupled to a bit line; andwherein during the program interval,the control circuitry causes channel boosting in a semiconductor strip of the semiconductor strips between (i) part of the semiconductor strip controlled by the selected word line and (ii) part of the semiconductor strip controlled by the first select line, andthe control circuitry does not cause channel boosting in the semiconductor strip between (i) part of the semiconductor strip controlled by the switching word line and (ii) part of the semiconductor strip controlled by the second select line. 12. The memory of claim 1, further comprising: memory cells arranged in a second series in a semiconductor strip of the semiconductor strips, wherein word lines in the plurality of word lines are coupled to corresponding memory cells in the second series of memory cells;a first select line controlling a first access transistor coupled to the first end of the second series; anda second select line controlling a second access transistor coupled to the second end of the second series; andwherein during the program interval, the control circuitry deselects the second series from programming, andthe control circuitry causes channel boosting in the semiconductor strip of the second series between (i) part of the semiconductor strip of the second series controlled by the first select line and (ii) part of the semiconductor strip of the second series controlled by the second select line, except for part of the semiconductor strip of the second series controlled by the switching word line. 13. The memory of claim 1, further comprising: a first select line controlling a first access transistor coupled to the first end of the series, the first end coupled to a source line; anda second select line controlling a second access transistor coupled to the second end of the series, the second end coupled to a bit line; andwherein during the program interval,the control circuitry causes channel boosting in a semiconductor strip of the semiconductor strips between (i) part of the semiconductor strip controlled by the selected word line and (ii) part of the semiconductor strip controlled by the second select line, andthe control circuitry does not cause channel boosting in the semiconductor strip between (i) part of the semiconductor strip controlled by the switching word line and (ii) part of the semiconductor strip controlled by the first select line. 14. The memory of claim 1, further comprising: memory cells arranged in a second series in a semiconductor strip of the semiconductor strips, wherein word lines in the plurality of word lines are coupled to corresponding memory cells in the second series of memory cells;a first select line controlling a first access transistor coupled to the first end of the second series; anda second select line controlling a second access transistor coupled to the second end of the second series; andwherein during the program interval, the control circuitry deselects the second series from programming, andthe control circuitry does not cause channel boosting in the semiconductor strip of the second series between part of the semiconductor strip of the second series controlled by the first select line, and part of the semiconductor strip of the second series controlled by the second select line. 15. A method comprising: programming a selected memory cell in a selected level of a three-dimensional array of memory cells and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting, and by applying a program disturb relief voltage to a program disturb relief word line to reduce program disturb during at least part of the program interval, another word line in between the selected word line and the program disturb relief word line, the program disturb relief voltage being less than drain-side pass voltages and source-side pass voltages, andwherein the array includes semiconductor strips on which memory cells are arranged in series, and including programming the selected memory cell during a program interval by: biasing one of a first end and a second end of the series of memory cells to a drain side voltage, and another of the first end and the second end to a source side voltage during the program interval,applying the drain-side pass voltages to a first subset of the plurality of word lines between the selected word line and said one of the first end and the second end during the program interval,applying the source-side pass voltages to a second subset of the plurality of word lines between the selected word line and said other of the first end and the second end during the program interval,applying a program voltage to the selected word line during the program interval; andapplying a switching voltage to a switching word line of the plurality of word lines and to a corresponding memory cell of the series of memory cells to control hot-carrier programming during the program interval, the switching word line being the another word line adjacent to the selected word line, and the corresponding memory cell adjacent to the selected memory cell. 16. The method of claim 15, wherein the program interval includes a first program stage and a second program stage. 17. The method of claim 16, wherein during the first stage the selected memory cell undergoes at least hot-carrier generation, and during the second stage the selected memory cell undergoes at least Fowler-Nordheim carrier injection. 18. The method of claim 16, wherein the switching voltage is a first switching voltage during the first program stage and a second switching voltage during the second program stage, and the first switching voltage and the second switching voltage have opposite polarities. 19. The method of claim 15, wherein the program disturb relief voltage is applied to the program disturb relief word line of the plurality of word lines and to another corresponding memory cell of the series of memory cells to reduce program disturb during at least part of the program interval, said another corresponding memory cell adjacent to the corresponding memory cell. 20. The method of claim 15, wherein the program voltage is equal to the drain-side pass voltages and the source-side pass voltages. 21. The method of claim 15, wherein during the program interval, the selected memory cell undergoes source-side boosting of hot-carrier programming of the selected memory cell. 22. The method of claim 15, wherein during the program interval, the selected memory cell undergoes drain-side boosting of hot-carrier programming of the selected memory cell. 23. A memory comprising: a three-dimensional array of memory cells having a plurality of levels of memory cells;a plurality of word lines, and a plurality of bit lines; and control circuitry coupled to the plurality of word lines and the plurality of bit lines, adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while applying a program disturb relief voltage to a program disturb relief word line, the program disturb relief voltage being less than drain-side pass voltages and source-side pass voltages, another word line in between the selected word line and the program disturb relief word line, andwherein the array includes semiconductor strips on which memory cells are arranged in series, and including programming the selected memory cell during the program interval by: biasing one of a first end and a second end of the series of the memory cells in the series to a drain side voltage, and another of the first end and the second end to a source side voltage during the program interval,applying the drain-side pass voltages to a first subset of the plurality of word lines between the selected word line and said one of the first end and the second end during the program interval,applying the source-side pass voltages to a second subset of the plurality of word lines between the selected word line and said other of the first end and the second end during the program interval,applying a program voltage to the selected word line during the program interval; andapplying a switching voltage to the switching word line of the plurality of word lines and to a corresponding memory cell of the memory cells in the series to control hot-carrier programming during at least part of the program interval, the switching word line being the another word line adjacent to the selected word line, and the corresponding memory cell adjacent to the selected memory cell.
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이 특허에 인용된 특허 (15)
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