Computer or microchip with its system bios protected by one or more internal hardware firewalls
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-021/70
H04L-029/06
G06F-021/74
A01N-025/30
G06F-009/50
G06F-011/16
G06F-015/76
G06F-021/00
H04L-012/26
H04L-029/08
G06F-011/30
출원번호
US-0328587
(2014-07-10)
등록번호
US-9172676
(2015-10-27)
발명자
/ 주소
Ellis, Frampton E.
출원인 / 주소
Ellis, Frampton E.
대리인 / 주소
Mendelsohn, Drucker & Dunleavy, P.C.
인용정보
피인용 횟수 :
0인용 특허 :
196
초록▼
A computer or microchip, comprising at least one protected portion, at least one network portion a system BIOS located in a first protected portion, and at least one internal hardware firewall located between the first protected portion and a first said network portion. The first protected portion b
A computer or microchip, comprising at least one protected portion, at least one network portion a system BIOS located in a first protected portion, and at least one internal hardware firewall located between the first protected portion and a first said network portion. The first protected portion being protected by at least a first internal hardware firewall, said first network portion having a connection for a network of computers including the World Wide Web and/or the Internet; the first internal hardware firewall denies access to at least said first protected portion of said computer or microchip from the network. The computer or microchip also includes hardware network communications components located in the first network portion and one or more microprocessors that are not hardware network communications components, located in the first network portion and are separate from the at least one internal hardware firewall. The location of at least the first internal hardware firewall permits unrestricted access by the network to the first network portion so that processing operations other than network communications and firewall operations conducted by said computer or microchip with the network are executed by one or more of said microprocessors in said first network portion.
대표청구항▼
1. A computer or microchip, comprising: at least one protected portion;at least one network portion;a system BIOS of both at least a part of a first said protected portion and at least a part of a first said network portion of the computer or microchip, the system BIOS being located in the first sai
1. A computer or microchip, comprising: at least one protected portion;at least one network portion;a system BIOS of both at least a part of a first said protected portion and at least a part of a first said network portion of the computer or microchip, the system BIOS being located in the first said protected portion of the computer or microchip;at least one internal hardware firewall located between the first protected portion of said computer or microchip and the first said network portion of said computer or microchip, said first protected portion being protected by at least a first said internal hardware firewall, said first network portion having a connection for a network of computers including the World Wide Web and/or the Internet; at least said first internal hardware firewall denies access to at least said first protected portion of said computer or microchip from said network of computers;hardware network communications components located in said first network portion of said computer or microchip; andone or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors that are not hardware network communications components, wherein said one or more microprocessors are located in said first network portion of said computer or microchip and are separate from said at least one internal hardware firewall. 2. The computer or microchip of claim 1, wherein the system BIOS is flash memory. 3. The computer or microchip of claim 1, wherein the system BIOS is protected by at least an additional said internal hardware firewall. 4. The computer or microchip of claim 1, wherein the system BIOS is protected by at least three said internal hardware firewalls. 5. The computer or microchip of claim 1, further comprising a master controlling device that controls the computer or microchip. 6. The computer or microchip of claim 5, wherein the master controlling device of said computer or microchip is located in said first protected portion of said computer or microchip. 7. The computer or microchip of claim 1, further comprising at least one microprocessor located in said first protected portion of said computer or microchip; and wherein said at least one microprocessor located in said first protected portion of said computer or microchip is separate from said at least one internal hardware firewall and said at least said first internal hardware firewall also denies access to said at least at least one microprocessor located in said first protected portion of said computer or microchip by the network of computers. 8. The computer or microchip of claim 1, wherein the location of at least said first internal hardware firewall permits unrestricted access by said network of computers to said first network portion of said computer or microchip so that processing operations other than network communications and firewall operations conducted by said computer or microchip with the network of computers are executed by one or more of said microprocessors in said first network portion of said computer or microchip. 9. The computer or microchip of claim 1, wherein the system BIOS is the system BIOS of both the first said protected portion and the first said network portion of the computer or microchip. 10. A computer or microchip comprising: at least one protected portion;at least one network portion having a connection for a network of computers;a system BIOS of both at least a part of a first said protected portion and at least a part of a first said network portion of the computer or microchip located in the first said protected portion of the computer or microchip; andat least one internal hardware firewall located so that one or more or at least two or four or eight or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors of the computer or microchip are not protected by at least a first said internal hardware firewall; and said one more microprocessors that are not protected by at least said first internal hardware firewall are separate from hardware network communications components and said at least one internal hardware firewall; andat least said first said internal hardware firewall denies access to said first protected portion of said computer or microchip from said network of computers. 11. The computer or microchip of claim 10, wherein the computer or microchip is a personal computer or microchip configured for control by an individual personal user to communicate with the network of computers; and at least said first internal hardware firewall, by its location, permits unrestricted access by the network of computers to said one or more microprocessors that are not protected by at least said first internal hardware firewall, so that processing operations controlled by said personal user, other than network communication and firewall operations, that are conducted by said computer or microchip with the network of computers are executed by one or more said microprocessors that are not protected by at least said first internal hardware firewall. 12. The computer or microchip of claim 10, wherein the system BIOS is flash memory. 13. The computer or microchip of claim 10, wherein the system BIOS is protected by at least an additional said internal hardware firewall. 14. The computer or microchip of claim 10, wherein the system BIOS is protected by at least three said internal hardware firewalls. 15. The computer or microchip of claim 10, further comprising a master controlling device that controls the computer or microchip. 16. The computer or microchip of claim 15, wherein the master controlling device of said computer or microchip is located in said first protected portion of said computer or microchip. 17. The computer or microchip of claim 10, further comprising at least one microprocessor located in said first protected portion of said computer or microchip; and wherein said at least one microprocessor located in said first protected portion of said computer or microchip is separate from said at least one internal hardware firewall and at least said first internal hardware firewall denies access to said at least one microprocessor located in said first protected portion of said computer or microchip by the network of computers. 18. The computer or microchip of claim 10, further comprising at least one sound component located in said first network portion of the computer or microchip and said at least one sound component is separate from said at least one internal hardware firewall. 19. The computer or microchip of claim 10, further comprising at least one video component located in said first network portion of the computer or microchip and said at least one video component is separate from said at least one internal hardware firewall. 20. The computer or microchip of claim 10, further comprising at least one graphics component located in said first network portion of the computer or microchip and said at least one graphics component is separate from said at least one internal hardware firewall. 21. The computer or microchip of claim 10, further comprising at least one hard drive component located in said first network portion of the computer or microchip and said at least one hard drive component is separate from said at least one internal hardware firewall. 22. The computer or microchip of claim 10, further comprising at least one optical disk drive component located in said first network portion of the computer or microchip and said at least one optical disk drive is separate from said at least one internal hardware firewall. 23. The computer or microchip of claim 10, further comprising at least one flash memory component located in said first network portion of the computer or microchip and said at least one flash memory component is separate from said at least one internal hardware firewall. 24. The computer or microchip of claim 10, wherein said processing operations include network browsing functions. 25. The computer or microchip of claim 24, wherein said network browsing functions are selected from the group consisting of World Wide Web or Internet searching, email and conferencing. 26. The computer or microchip of claim 10, wherein the location of at least said first internal hardware firewall permits unrestricted access by said network of computers to a first said network portion of said computer or microchip so that processing operations other than network communications and firewall operations conducted by said computer or microchip with the network of computers are executed by one or more of said microprocessors in said first network portion of said computer or microchip. 27. The computer or microchip of claim 10, wherein the system BIOS is the system BIOS of both the first said protected portion and the first said network portion of the computer or microchip. 28. A computer or microchip, comprising: at least one protected portion;at least one network portion;a system BIOS of both at least a part of a first protected portion and at least a part of a first said network portion of the computer or microchip located in the first said protected portion of the computer or microchip; andat least one internal hardware firewall located between the first protected portion of said computer or microchip and the first said network portion of said computer or microchip, said first protected portion being protected by at least a first said internal hardware firewall; said first network portion including a connection for a network of computers including the World Wide Web and/or the Internet;network communications components located in said first network portion of said computer or microchip; at least said first internal hardware firewall denies access to said first protected portion from communications originating from said network of computers;said first network portion of said computer or microchip being located between at least said first internal hardware firewall and a connection of said computer or microchip to said network of computers; andone or more or at least two or four or eight or 14 or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors located in said first network portion of said computer or microchip; said one or more microprocessors located in said first network portion being separate from said network communications components;said one or more microprocessors located in said first network portion and said network communications components being separate from said at least one internal hardware firewall. 29. The computer or microchip of claim 28, wherein the system BIOS is flash memory. 30. The computer or microchip of claim 28, wherein the system BIOS is protected by at least an additional said internal hardware firewall. 31. The computer or microchip of claim 28, wherein the system BIOS is protected by at least three said internal hardware firewalls. 32. The computer or microchip of claim 28, further comprising a master controlling device that controls the computer or microchip. 33. The computer or microchip of claim 32, wherein the master controlling device of said computer or microchip is located in said first protected portion of said computer or microchip. 34. The computer or microchip of claim 28, further comprising at least one microprocessor located in said first protected portion of said computer or microchip; and wherein said at least one microprocessor located in said first protected portion of said computer or microchip is separate from said at least one internal hardware firewall and at least said first internal hardware firewall denies access to said at least one microprocessor located in said first protected portion of said computer or microchip by the network of computers. 35. The computer or microchip of claim 28, wherein the computer or microchip initiates a request to said network of computers for execution of one or more shared processing operations conducted by said computer or microchip with the network of computers that are executed at least by one or more said microprocessors located in said first network portion of the computer or microchip. 36. The computer or microchip of claim 28, wherein said computer or microchip performs World Wide Web or Internet browsing with the network of computers and processing performed by the computer or microchip for said World Wide Web or Internet browsing with the network of computers is executed at least by one or more said microprocessors located in said first network portion of the computer or microchip. 37. The computer or microchip of claim 28, wherein said computer or microchip is configured to function as a node in a computer system with many such nodes in which one or more shared processing operations conducted by said computer or microchip with the network of computers are executed at least by one or more said microprocessors located in said first network portion of the computer or microchip. 38. The computer or microchip of claim 28, and wherein one or more shared processing operations initiated by said computer or microchip with the network of computers are executed at least by one or more said microprocessors located in said first network portion of the computer or microchip. 39. The computer or microchip of claim 28, wherein one or more search operations initiated by said computer or microchip with the network of computers are executed at least by one or more said microprocessors located in said first network portion of the computer or microchip. 40. The computer or microchip of claim 28, wherein at least said first internal hardware firewall, by its location, permits unrestricted access by said network of computers to said first network portion of said computer or microchip, and wherein one or more shared processing operations conducted by said computer or microchip with the network of computers is executed by at least by one or more said microprocessors located in said first network portion of the computer or microchip. 41. The computer or microchip of claim 28, wherein the system BIOS is the system BIOS of both the first said protected portion and the first said network portion of the computer or microchip.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (196)
Nielsen Keith E. (Redondo Beach CA), Active energy control for diode pumped laser systems using pulsewidth modulation.
Benkeser Donald E. (Naperville IL) Cyr Joseph B. (Aurora IL) Greenberg Albert G. (Millburn NJ) Wright Paul E. (Basking Ridge NJ), Adaptive job scheduling for multiprocessing systems with master and slave processors executing tasks with opposite antic.
Bonneau ; Jr. Walt C. (Missouri City TX) Guttag Karl (Missouri City TX) Gove Robert (Dallas TX), Architecture of a chip having multiple processors and multiple memories.
Russell David S. (Minneapolis MN) Fischer Larry G. (Waseca MN) Wala Philip M. (Waseca MN) Ratliff Charles R. (Crystal Lake IL) Brennan Jeffrey (Waseca MN), Cellular communications system with centralized base stations and distributed antenna units.
Naedel Richard G. (Rockville MD) Harris David B. (Columbia MD) Uehling Mark (Bowie MD), Chassis and personal computer for severe environment embedded applications.
Berkowitz David B. (Palo Alto CA) Hao Ming C. (Los Altos CA) Lieu Hung C. (Santa Clara CA) Snow Franklin D. (Saratoga CA), Collaborative computing system using pseudo server process to allow input from different server processes individually a.
Sumimoto Shinji (Kawasaki JPX), Computer resource distributing method and system for distributing a multiplicity of processes to a plurality of computer.
Lindman Richard S. (3708 17th Ave. South Minneapolis MN 55407) Lindman Richard P. (7625 18th Ave. South Richfield MN 55423) Myers Edward D. (4440 Denton Way Inver Grove Heights MN 55075), Computer security system.
Passera Anthony ; Thorp John R. ; Beckerle Michael J. ; Zyszkowski Edward S. A., Computer system and computerized method for partitioning data for parallel processing.
Jones Oliver (Andover MA) Deshon Mary (Winthrop MA) Ericsson Staffan (Brookline MA) Flach James (Cave Creek AZ), Computer teleconferencing method and apparatus.
Ellis, III, Frampton E., Computers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartments.
Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall and an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary inner hardware firewalls.
Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewalls.
Glick James A. (Granite Shoals TX) Graczyk Ronald B. (Round Rock TX) Nurick Albert F. (Austin TX) Fraley Brittain D. (Austin TX), Computing and multimedia entertainment system.
Leung Wing Y. (Cupertino CA) Hsu Fu-Chieh (Saratoga CA), Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale in.
Morley Richard E. (Greenville NH), Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and met.
Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Riegelhaupt Norbert H. (Framingham MA), Dual-rail processor with error checking at single rail interfaces.
Rosenberry Steven (Reading PA), Dynamic fault-tolerant parallel processing system for performing an application function with increased efficiency using.
Pian Chao-Kuang (Anaheim CA) Habereder Hans L. (Orange CA), Dynamic task allocation in a multi-processor system employing distributed control processors and distributed arithmetic.
Pezeshki Bardia (Huntington Beach CA) Harris ; Jr. James S. (Stanford CA), Electrostatically tunable optical device and optical interconnect for processors.
Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Fully scalable parallel processing system having asynchronous SIMD processing.
Nguyen Tam M. (Valhalla NY) Rana Deepak (Yorktown Heights NY) Ruiz Antonio (Yorktown Heights NY) Willner Barry E. (Briarcliff Manor NY), Hybrid digital/analog multimedia hub with dynamically allocated/released channels for video processing and distribution.
Fucito Michele (Meta ITX) Recchia Maruo (Rome ITX) Puglia Silvestro (Pomezia ITX) Mariani Claudio (Rome ITX) Colangeli Giulio (Gerenzano di Roma ITX) Rotunno Antonio (Salerno ITX), Interface unit for dynamically configuring a buffer in different modes to store data transfers based upon different conn.
Guy Charles B. (Hillsboro OR) Cadambi Sudarshan B. (Beaverton OR) Gutmann Michael J. (Portland OR) Bhasker Narjala (Portland OR) Trethewey Jim R. (Beaverton OR) McArdle Brian J. (Beaverton OR), Interrupt distribution scheme for a computer bus.
Wade Jon P. ; Cassiday Daniel R. ; Lordi Robert D. ; Steele ; Jr. Guy Lewis ; St. Pierre Margaret A. ; Wong-Chan Monica C. ; Abuhamdeh Zahi S. ; Douglas David C. ; Ganmukhi Mahesh N. ; Hill Jeffrey V, Massively parallel computer including auxiliary vector processor.
Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L., Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network an.
Bruckert William (Northboro MA) Kovalcin David (Grafton MA) Bissett Thomas D. (Derry NH) Munzer John (Brookline MA) Mazur Dennis (Worcester MA) Mott ; Jr. Peter R. (Worcester MA) Dearth Glenn A. (Hud, Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having.
Ault Donald Fred ; Bender Ernest Scott ; Spiegel Michael Gary, Method and apparatus for creating a security environment for a user task in a client/server system.
Anderson Mark Stephen,AUX ; Griffin John Edmund,AUX ; North Christopher James Guildford,AUX ; Yesberg John Desborough,AUX ; Yiu Kenneth Kwok-Hei,AUX ; Milner Robert Brunyee,AUX, Method and means for interconnecting different security level networks.
Kisor Greg, Method and system including a central computer that assigns tasks to idle workstations using availability schedules and computational capabilities.
Farnworth Warren M. (Boise ID) Duesman Kevin (Boise ID) Heitzeberg Ed (Boise ID), Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers.
Rausch Dieter (Karlsruhe DEX), Method for preventing an overload when starting a multicomputer system and multicomputer system for carrying out said me.
Shorter David U. (Lewisville TX), Method for scheduling execution of distributed application programs at preset times in an SNA LU 6.2 network environment.
Harris Jonathan P. (Littleton MA) Leibholz Daniel (Watertown MA) Miller Brad (Westborough MA), Method of dynamically allocating processors in a massively parallel processing system.
Ellis, Frampton E., Method of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Ellis, Frampton E., Methods of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Hu Ming K. (Syracuse NY) Jia Yau G. (Nanjing ; Jiangsu CNX), Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors.
Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce, N-dimensional modified hypercube.
Hodge Winston W. (Yorba Linda CA) Taylor Lawrence E. (Anaheim CA), Near-video-on-demand digital video distribution system utilizing asymmetric digital subscriber lines.
Georgiou,Christos J.; Gregurick,Victor L.; Nair,Indira; Salapura,Valentina, Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus.
Hinsley Christopher Andrew,GBX, Operating system for use with computer networks incorporating one or more data processors linked together for parallel p.
Chin Danny (Robbinsville NJ) Sauer Donald J. (Allentown NJ) Meyerhofer Dietrich (Princeton NJ) Katsuki Kazuo (Hyogo JPX), Parallel digital processing system using optical interconnection between control sections and data processing sections.
Beatty Harry J. (Clinton Corners NY) Elmendorf Peter C. (Kingston NY) Gillis Roland R. (Ulster Park NY) Pramanick Ira (Wappingers Falls NY), Parallel execution of a complex task partitioned into a plurality of entities.
Beatty Harry John ; Elmendorf Peter Claude ; Gillis Roland Roberto ; Pramanick Ira, Parallel execution of a complex task partitioned into a plurality of entities.
Policard, Claude M, Personal computer having a master computer system and an internet computer system and monitoring a condition of said master and internet computer systems.
Bahr James E. (Rochester MN) Corrigan Michael J. (Rochester MN) Knipfer Diane L. (Rochester MN) McMahon Lynn A. (Rochester MN) Metzger Charlotte B. (Elgin MN), Process for dispatching tasks among multiple information processors.
Nelson Darul J. ; Noval James V. ; Suarez Ricardo E. ; Aghazadeh Mostafa A., Processor card assembly including a heat sink attachment plate and an EMI/ESD shielding cage.
Gregerson Daniel P. ; Farrell David R. ; Gaitonde Sunil S. ; Ahuja Ratinder P. ; Ramakrishnan Krish ; Shafiq Muhammad ; Wallis Ian F., Scalable distributed computing environment.
Browne Hendrik A., Secure computer system and method of providing secure access to a computer system including a stand alone switch operable to inhibit data corruption on a storage device.
Ohta Hiroyuki,JPX ; Miura Hideo,JPX ; Usami Mitsuo,JPX ; Kametani Masatsugu,JPX ; Zen Munetoshi,JPX ; Okamoto Noriaki,JPX, Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same.
Danahy John J. ; Kinney Daryl F. ; Pulsinelli Gary S. ; Rose Lawrence J. ; Kumar Navaneet, Service-centric monitoring system and method for monitoring of distributed services in a computing network.
Hoover Russell D. (Rochester MN) Willis John C. (Rochester MN) Baldus Donald F. (Mazeppa MN) Ziegler Frederick J. (Rochester MN) Liu Lishing (Pleasantville NY), System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data p.
Teper Jeffrey A. ; Koneru Sudheer ; Mangione Gordon ; Balaz Rudolph ; Contorer Aaron M. ; Chao Lucy, System and method for providing trusted brokering services over a distributed network.
Chasek Norman E. (24 Briar Brae Rd. Stamford CT 06903), System for developing real time economic incentives to encourage efficient use of the resources of a regulated electric.
Leclercq Thierry (Paris FRX) Sallio Patrick (Thorigne-Fouillard FRX), System for management of the usage of data consultations in a telecommunication network.
Choquier Philippe,FRX ; Peyroux Jean-Francios ; Griffin William J., System for on-line service in which gateway computer uses service map which includes loading condition of servers broad.
Baehr Geoffrey G. ; Danielson William ; Lyon Thomas L. ; Mulligan Geoffrey ; Patterson Martin,FRX ; Scott Glenn C. ; Turbyfill Carolyn, System for packet filtering of data packets at a computer network interface.
Shwed Gil,ILX ; Kramer Shlomo,ILX ; Zuk Nir,ILX ; Dogon Gil,ILX ; Ben-Reuven Ehud,ILX, System for securing the flow of and selectively modifying packets in a computer network.
Padgaonkar Ajay J. (Phoenix AZ) Mitra Sumit K. (Tempe AZ), System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory.
Kraft Reiner ; Lu Qi ; Wisebond Marat, Task distribution processing system and the method for subscribing computers to perform computing tasks during idle time.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.