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Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that

Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.

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1. A method for accessing a memory, comprising: storing data in an array of memory cells, wherein each memory cell comprises a first access device, a second access device, and a storage element connected to the first and second access devices;accessing a plurality of memory cells along a row directi

1. A method for accessing a memory, comprising: storing data in an array of memory cells, wherein each memory cell comprises a first access device, a second access device, and a storage element connected to the first and second access devices;accessing a plurality of memory cells along a row direction of the array of memory cells using a first arrangement of access wiring comprising wordlines and bitlines connected to the memory cells, wherein the word lines of the first arrangement of access wiring are configured to control activation and deactivation of the first access devices of the memory cells, and wherein the bit lines of the first arrangement of access wiring are switchably connected to the storage elements of the memory cells through activation of the first access devices; andaccessing a plurality of memory cells along a column direction of the array of memory cells using a second arrangement of access wiring comprising word lines and bit lines connected to the memory cells, wherein the word lines of the second arrangement of access wiring are configured to control activation and deactivation of the second access devices of the memory cells, and wherein the bit lines of the second arrangement of access wiring are switchably connected to the storage elements of the memory cells through activation of the second access devices;wherein the word lines of the first arrangement of access wiring are disposed orthogonal to the word lines of the second arrangement of access wiring, and wherein the bitlines of the first arrangement of access wiring are disposed orthogonal to the bit lines of the second arrangement of access wiring, andwherein accessing the plurality of memory cells along the row direction and accessing the plurality of memory cells along the column direction are each performed using a single access operation to enable independent access to rows and columns of memory cells in the array of memory cells. 2. The method of claim 1, wherein the array of memory cells and the first and second arrangements of access wiring are formed on a single chip. 3. The method of claim 1, wherein the first arrangement of access wiring is formed on a first chip, wherein the second arrangement of access wiring is formed on a second chip, separate from the first chip, and wherein the array of memory cells is formed on the first chip. 4. The method of claim 3, wherein the first and second chips are connected in a stacked structure, and wherein the first and second chips comprise via connections to connect the second access devices on the second chip to respective ones of the storage elements of the array of memory cells on the first chip. 5. The method of claim 1, wherein the memory is a cache memory. 6. The method of claim 1, wherein the memory is a main system memory. 7. A method for accessing a memory, comprising: storing data in a first array of memory cells, each memory cell in the first array of memory cells comprising a storage element, a first access device connected to the storage element, and a second access device connected to the storage element;performing a first memory access operation to access data in the first array of memory cells using a first arrangement of access wiring connected to the memory cells, wherein the first arrangement of access wiring comprises word lines and bit lines, wherein the word lines of the first arrangement of access wiring are configured to control activation and deactivation of the first access devices of the memory cells in the first array of memory cells, and wherein the bit lines of the first arrangement of access wiring are switchably connected to the storage elements of the memory cells in the first array of memory cells through activation of the first access devices;performing a second memory access operation to access data in the first array of memory cells using a second arrangement of access wiring connected to the memory cells, wherein the second arrangement of access wiring comprises word lines and bit lines, wherein the word lines of the second arrangement of access wiring are configured to control activation and deactivation of the second access devices of the memory cells in the first array of memory cells, and wherein the bit lines of the second arrangement of access wiring are switchably connected to the storage elements of the memory cells in the first array of memory cells through activation of the second access devices;wherein the word lines of the first arrangement of access wiring extend in a first direction which is non parallel to a second direction in which the word lines of the second arrangement of access wiring extend; andwherein the first and second memory access operations are performed independently to access different patterns of data from memory cells of the first array of memory cells along the first and second directions. 8. The method of claim 7, wherein word lines of the first arrangement of access wiring are arranged orthogonal to word lines of the second arrangement of access wiring. 9. The method of claim 7, wherein word lines of at least one of the first arrangement of access wiring and the second arrangement of access wiring extend diagonally across the first array of memory cells. 10. The method of claim 7, wherein word lines of at least one of the first arrangement of access wiring and the second arrangement of access wiring extend in a column-shifted direction. 11. The method of claim 7, further comprising: storing data in a second array of memory cells, each memory cell in the second array of memory cells comprising a storage element and a third access device connected to the storage element;performing a third memory access operation to access data in the second array of memory cells using a third arrangement of access wiring connected to the memory cells of the second array of memory cells, wherein the third arrangement of access wiring comprises word lines and bit lines wherein the word lines of the third arrangement of access wiring are configured to control activation and deactivation of the third access devices of the memory cells in the second array of memory cells, and wherein the bit lines of the third arrangement of access wiring are switchably connected to the storage elements of the memory cells in the second array of memory cells through activation of the third access devices; andperforming a fourth memory access operation to access data stored in a first memory cell of the first array of memory cells and data stored in a second memory cell of the second array of memory cells by: activating a vertical word line of a fourth arrangement of vertical wordlines, which is commonly connected to said first and second memory cells; andactivating a bit line of the third arrangement of access wiring and a bit line of either the first or second arrangement of access wiring to read out the data stored in the first and second memory cells. 12. The method of claim 11, wherein the third arrangement of word lines and bit lines has a same arrangement as at least one of the first arrangement and second arrangement of word lines and bit lines. 13. The method of claim 7, wherein the memory is a cache memory. 14. The method of claim 7, wherein the memory is a main system memory. 15. A method for accessing a memory, comprising: storing data in a first array of memory cells, each memory cell in the first array of memory cells comprising a storage element and a first access device connected to the storage element;storing data in a second array of memory cells, each memory cell in the second array of memory cells comprising a storage element and a second access device connected to the storage element;performing a first memory access operation to access data in the first array of memory cells using a first arrangement of access wiring connected to the memory cells, wherein the first arrangement of access wiring comprises word lines and bit lines wherein the word lines of the first arrangement of access wiring are configured to control activation and deactivation of the first access devices of the memory cells in the first array of memory cells, and wherein the bit lines of the first arrangement of access wiring are switchably connected to the storage elements of the memory cells in the first array of memory cells through activation of the first access devices;performing a second memory access operation to access data in the second array of memory cells using a second arrangement of access wiring connected to the memory cells, wherein the second arrangement of access wiring comprises word lines and bit lines wherein the word lines of the second arrangement of access wiring are configured to control activation and deactivation of the second access devices of the memory cells in the second array of memory cells, and wherein the bit lines of the second arrangement of access wiring are switchably connected to the storage elements of the memory cells in the second array of memory cells through activation of the second access devices; andperforming a third memory access operation to access data stored in a first memory cell of the first array of memory cells and data stored in a second memory cell of the second array of memory cells by: activating a vertical word line of a third arrangement of vertical word lines, which is commonly connected to said first and second memory cells; andactivating a bit line of the first arrangement of access wiring and a bit line of the second arrangement of access wiring to read out the data stored in the first and second memory cells. 16. The method of claim 15, wherein the word lines and bit lines of the first arrangement of access wiring have a same arrangement as the word lines and bit lines of the second arrangement of access wiring. 17. The method of claim 15, wherein the word lines and bit lines of the first arrangement of access wiring have an arrangement that is different than the arrangement of the word lines and bit lines of the second arrangement of access wiring. 18. The method of claim 15, wherein the memory is one of a cache memory and a main system memory. 19. The method of claim 15, wherein the first array of memory cells and the first arrangement of access wiring are formed on a first chip, wherein the second array of memory cells and the second arrangement of access wiring are formed on a second chip, wherein the first and second chips are connected in a stacked structure and comprise via connections which form the vertical word lines of the third arrangement of vertical word lines.