A 3D IC based mobile system including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors a
A 3D IC based mobile system including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a plurality of thermal paths between the second mono-crystallized transistors and a heat removal apparatus, where at least one of the plurality of thermal paths includes a thermal contact adapted to conduct heat and not conduct electricity; and a heat spreader layer between the second layer and the at least one metal layer.
대표청구항▼
1. A 3D IC based mobile system comprising: a first semiconductor layer comprising first mono-crystallized transistors, wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising aluminum or copper;a second layer comprising second mono-crystallized tran
1. A 3D IC based mobile system comprising: a first semiconductor layer comprising first mono-crystallized transistors, wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising aluminum or copper;a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer, wherein said at least one metal layer is in-between said first semiconductor layer and said second layer;a plurality of thermal paths between said second mono-crystallized transistors and a heat removal apparatus, wherein at least one of said plurality of thermal paths comprises a thermal contact adapted to conduct heat and not conduct electricity; anda heat spreader layer between said second layer and said at least one metal layer. 2. A system according to claim 1, further comprising: a first alignment mark and a second alignment mark; and wherein said first semiconductor layer comprises said first alignment mark and said second layer comprises said second alignment mark,wherein at least one of said plurality of thermal paths comprises a via through said second layer, andwherein said via is aligned to said first alignment mark and said second alignment mark. 3. A system according to claim 1, wherein said second mono-crystallized transistors comprise horizontally oriented transistors. 4. A system according to claim 1, further comprising: a power distribution network to provide power to said second mono-crystallized transistors, wherein said power distribution network provides a network thermal path from at least one of said second mono-crystallized transistors to said heat removal apparatus, andwherein said network thermal path comprises a second thermal contact adapted to conduct heat and not conduct electricity. 5. A system according to claim 1, further comprising: a programmable interconnect structure disposed between said first semiconductor layer and said second layer, wherein at least one of said second mono-crystallized transistors is connected for programming of said programmable interconnect structure. 6. A system according to claim 1, wherein said plurality of thermal paths comprise vias through said second layer, andwherein at least one of said vias is less than 150 nm in diameter. 7. A system according to claim 1 wherein at least one of said second mono-crystallized transistors is one of: (i) a recessed-channel transistor (RCAT);(ii) a junction-less transistor;(iii) a replacement-gate transistor;(iv) a Finfet transistor; or(v) a double gate transistor. 8. A 3D IC based mobile system comprising: a first semiconductor layer comprising first mono-crystallized transistors, wherein said first mono-crystallized transistors are interconnected by a plurality of metal layers comprising aluminum or copper, andwherein said plurality of metal layers comprises at least one programmable interconnect structure;a second layer comprising second mono-crystallized transistors and overlaying said plurality of metal layers, wherein said second layer is between 3 nm and 200 nm in thickness,wherein said plurality of metal layers is in-between said first semiconductor layer and said second layer, andwherein at least one of said second mono-crystallized transistors is connected for programming of said programmable interconnect structure; anda power distribution network to provide power to said second mono-crystallized transistors, wherein said power distribution network provides a first thermal path from at least one of said second mono-crystallized transistors to a heat removal apparatus, andwherein said first thermal path comprises a thermal contact adapted to conduct heat and not conduct electricity. 9. A system according to claim 8, further comprising: a heat spreader layer between said second layer and said plurality of metal layers. 10. A system according to claim 8, wherein at least one of said second mono-crystallized transistors is an N-type transistor and at least one of said second mono-crystallized transistors is a P-type transistor. 11. A system according to claim 8, further comprising: a plurality of second thermal paths between said second mono-crystallized transistors and said heat removal apparatus, wherein at least one of said plurality of second thermal paths comprises a second thermal contact adapted to conduct heat and not conduct electricity. 12. A system according to claim 8, further comprising: a back-gate structure for at least one of said second mono-crystallized transistors. 13. A system according to claim 8 wherein at least one of said second mono-crystallized transistors is one of: (i) a recessed-channel transistor (RCAT);(ii) a junction-less transistor;(iii) a replacement-gate transistor;(iv) a Finfet transistor; or(v) a double gate transistor. 14. A 3D IC based mobile system comprising: a first semiconductor layer comprising first mono-crystallized transistors, wherein said first mono-crystallized transistors are interconnected by a plurality of metal layers comprising aluminum or copper;a second layer comprising second mono-crystallized transistors and overlaying said plurality of metal layers, wherein said plurality of metal layers is in-between said first semiconductor layer and said second layer;a plurality of connection paths between said second mono-crystallized transistors and said first mono-crystallized transistors; andat least one repeater comprising said second mono-crystallized transistors, wherein said at least one repeater is coupled to a first portion of said plurality of metal layers and to a second portion of said plurality of metal layers,wherein said connection paths comprise vias through said second layer, andwherein at least one of said vias is less than 150 nm in diameter. 15. A system according to claim 14 wherein said second layer is between 3 nm and 200 nm in thickness. 16. A system according to claim 14, further comprising: a heat spreader layer between said second layer and said plurality of metal layers. 17. A system according to claim 14, further comprising: a power distribution network to provide power to said second mono-crystallized transistors, wherein said power distribution network provides a thermal path from at least one of said second mono-crystallized transistors to a heat removal apparatus, andwherein said thermal path comprises a thermal contact adapted to conduct heat and not conduct electricity. 18. A system according to claim 14, further comprising: a programmable interconnect structure disposed between said first semiconductor layer and said second layer, wherein at least one of said second mono-crystallized transistors is connected for programming of said programmable interconnect structure. 19. A system according to claim 14, further comprising: a plurality of thermal paths between said second mono-crystallized transistors and a heat removal apparatus, wherein said thermal path comprises a thermal contact, said thermal contact is adapted to conduct heat and not conduct electricity. 20. A system according to claim 14, wherein said second mono-crystallized transistors comprise horizontally oriented transistors. 21. A system according to claim 14 wherein at least one of said second mono-crystallized transistors is one of: (i) a recessed-channel transistor (RCAT);(ii) a junction-less transistor;(iii) a replacement-gate transistor;(iv) a Finfet transistor; or(v) a double gate transistor.
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Marmillion Patricia McGuinness ; Palagonia Anthony Michael ; Pierson Bernadette Ann ; Schmidt Dennis Arthur, Cooling method for silicon on insulator devices.
Abou-Khalil, Michel J.; Gauthier, Jr., Robert J.; Lee, Tom C.; Li, Junjun; Putnam, Christopher S.; Mitra, Souvick, Design structures for high-voltage integrated circuits.
Abadeer, Wagdi W.; Chatty, Kiran V.; Gauthier, Jr., Robert J.; Rankin, Jed H.; Shi, Yun; Tonti, William R., Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures.
Aronowitz Sheldon ; Puchner Helmut ; Kapre Ravindra A. ; Kimball James P., Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of sil.
Fitch Jon T. (Austin TX) Venkatesan Suresh (Austin TX) Witek Keith E. (Austin TX), Integrated circuit having both vertical and horizontal devices and process for making the same.
New,Bernard J.; Conn,Robert O.; Young,Steven P.; Young,Edel M., Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit.
Shimoto,Tadanori; Kikuchi,Katsumi; Matsui,Koji; Baba,Kazuhiro, Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device.
Vyvoda, Michael A.; Herner, S. Brad; Petti, Christopher J.; Walker, Andrew J., Inverted staggered thin film transistor with salicided source/drain structures and method of making same.
Rohatgi Ajeet (Murrysville PA) Rai-Choudhury Prosenjit (Export PA) Gigante Joseph R. (Beltsville MD) Singh Ranbir (State College PA) Fonash Stephen J. (State College PA), Low temperature process for annealing shallow implanted N+/P junctions.
Dawson Robert ; Fulford ; Jr. H. Jim ; Gardner Mark I. ; Hause Frederick N. ; Michael Mark W. ; Moore Bradley T. ; Wristers Derick J., Method and apparatus for in situ anneal during ion implant.
Iriguchi, Chiharu, Method for fabricating semiconductor device, and electro-optical device, integrated circuit and electronic apparatus including the semiconductor device.
Leas James Marc (South Burlington VT) Voldman Steven Howard (South Burlington VT), Method for forming a monolithic electronic module by dicing wafer stacks.
Zavracky Paul M. (Norwood MA) Zavracky Matthew (Attleboro MA) Vu Duy-Phach (Taunton MA) Dingle Brenda (Mansfield MA), Method for forming three dimensional processor using transferred thin film circuits.
Chan Kevin Kok ; D'Emic Christopher Peter ; Jones Erin Catherine ; Solomon Paul Michael ; Tiwari Sandip, Method for making bonded metal back-plane substrates.
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Harder Christoph S. (Zurich CHX) Jaeckel Heinz (Kilchberg CHX) Wolf Hans P. (Zurich CHX), Method of fabricating a self-aligned metal-semiconductor FET having an insulator spacer.
Norman Michael P. (Chandler AZ) Harvey ; III Thomas B. (Scottsdale AZ) Zhu Xiaodong T. (Chandler AZ), Method of fabricating an integrated multicolor organic led array.
Kwon, Jang yeon; Han, Min koo; Cho, Se young; Park, Kyung bae; Kim, Do young; Lee, Min cheol; Han, Sang myeon; Noguchi, Takashi; Park, Young soo; Jung, Ji sim, Method of fabricating poly-crystalline silicon thin film and method of fabricating transistor using the same.
Robert William McClelland ; Noa More Rensing ; Mark Bradley Spitzer ; Paul Daniel Aquilino ; Paul Martin Zavracky, Method of fabrication of a torsional micro-mechanical mirror system.
Anderson James M. (Huntington Beach CA) Coulson Andrew R. (Santa Monica CA) Demaioribus Vincent J. (Redondo Beach CA) Nicholas Henry T. (Redondo Beach CA), Method of making an adaptive configurable gate array.
Kang Sang-Won (Daejeon KRX) Yu Hyun-Kyu (Daejeon KRX) Kang Won-Gu (Daejeon KRX), Method of manufacturing a semiconductor device having buried elements with electrical characteristic.
Ho, ChiaHua; Lai, Erh Kun; Hsieh, Kuang Yeu, Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states.
Stephen Ross Forrest ; Mark Edward Thompson ; Paul Edward Burrows ; Dennis Matthew McCarty ; Linda Susan Sapochak ; Jon Andrew Cronin, Mixed vapor deposited films for electroluminescent devices.
Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Forrest Stephen Ross ; Thompson Mark Edward ; Burrows Paul Edward ; Sapochak Linda Susan ; McCarty Dennis Matthew, Multicolor organic light emitting devices.
Jang, Jae Hoon; Jung, Soon Moon; Kim, Jong Hyuk; Rah, Young Seop; Park, Han Byung, Non-volatile memory devices including etching protection layers and methods of forming the same.
Koh, Gwan-Hyeob; Ha, Dae-Won, Non-volatile memory devices including stacked NAND-type resistive memory cell strings and methods of fabricating the same.
Kim, Sarah E.; List, R. Scott; Kellar, Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
Kim,Sarah E.; List,R. Scott; Kellar,Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
Breitwisch, Matthew J.; Ditlow, Gary S.; Franceschini, Michele M.; Lastras-Montano, Luis A.; Montoye, Robert K.; Rajendran, Bipin, Resistive memory devices having a not-and (NAND) structure.
Thomas, Olivier; Batude, Perrine; Pouydebasque, Arnaud; Vinet, Maud, SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable.
Nemati Farid ; Plummer James D., Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches.
Farnworth,Warren M.; Wood,Alan G.; Hiatt,William M.; Wark,James M.; Hembree,David R.; Kirby,Kyle K.; Benson,Pete A., Semiconductor component having plate, stacked dice and conductive vias.
Saito Keishi (Nabari JPX) Fujioka Yasushi (Ueno JPX), Semiconductor device having a semiconductor region in which a band gap being continuously graded.
Mazur Carlos A. (Austin TX) Fitch Jon T. (Austin TX) Hayden James D. (Austin TX) Witek Keith E. (Austin TX), Semiconductor memory device and method of formation.
Zavracky Paul M. (Norwood MA) Fan John C. C. (Chestnut Hill MA) McClelland Robert (Norwell MA) Jacobsen Jeffrey (Hollister CA) Dingle Brenda (Norton MA) Spitzer Mark B. (Sharon MA), Single crystal silicon arrayed devices for display panels.
Iyer Subramanian S. ; Baran Emil ; Mastroianni Mark L. ; Craven Robert A., Single-etch stop process for the manufacture of silicon-on-insulator wafers.
Atkinson Gary M. (1012 - 7th St. ; #15 Santa Monica CA 90403) Courtney M. DuChesne (15127 Blackhawk Mission Hills CA 91345), Split collector vacuum field effect transistor.
Schuehrer,Holger; Hartig,Carsten; Bartsch,Christin; Frohberg,Kai, Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer.
Barbee Steven G. (Dover Plains NY) Leas James M. (Washington DC) Lloyd James R. (Fishkill NY) Nagarajan Arunachala (Wappingers Falls NY), Thin film semiconductor device and method for manufacture.
Chan, Victor; Guarini, Kathryn W.; Ieong, Meikei, Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers.
Alam, Syed M.; Elfadel, Ibrahim M.; Guarini, Kathryn W; Ieong, Meikei; Kudva, Prabhakar N.; Kung, David S.; Lavin, Mark A.; Rahman, Arifur, Three dimensional integrated circuit and method of design.
Takayama,Toru; Maruyama,Junya; Goto,Yuugo; Kuwabara,Hideaki; Yamazaki,Shunpei, Vehicle, display device and manufacturing method for a semiconductor device.
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