최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
---|---|
국제특허분류(IPC7판) |
|
출원번호 | US-0466335 (2009-05-14) |
등록번호 | US-9230910 (2016-01-05) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 1 인용 특허 : 476 |
A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section h
A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first layout structure, the second layout structure, or both the first and second layout structures. A dimension of the rectangular-shaped interlevel connection layout structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection layout structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second layout structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.
1. A method for creating a layout of a semiconductor device, comprising: processing a layout of a semiconductor device to identify a first linear-shaped gate electrode level layout structure that forms a gate electrode of a first transistor and a second linear-shaped gate electrode level layout stru
1. A method for creating a layout of a semiconductor device, comprising: processing a layout of a semiconductor device to identify a first linear-shaped gate electrode level layout structure that forms a gate electrode of a first transistor and a second linear-shaped gate electrode level layout structure that forms a gate electrode of a second transistor, each of the first and second linear-shaped gate electrode level layout structures oriented to extend lengthwise in a first direction, the first and second linear-shaped gate electrode level layout structures positioned next to each other such that their respective lengthwise-oriented centerlines are separated from each other by a gate electrode pitch as measured in a second direction perpendicular to the first direction;processing the layout of the semiconductor device to identify a first linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure;processing the layout of the semiconductor device to identify a second linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure;processing the layout of the semiconductor device to identify a third linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure;determining a size of the first linear-shaped gate electrode level layout structure as measured in the second direction;creating a first rectangular-shaped interlevel connection layout structure to have a horizontal cross-section with a first size as measured in the first direction and a second size as measured in the second direction, the second size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure at least twice the first size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure, and the second size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure larger than twice the size of the first linear-shaped gate electrode level layout structure as measured in the second direction;modifying the layout of the semiconductor device by positioning the first rectangular-shaped interlevel connection layout structure in a substantially centered manner on the first linear-shaped gate electrode level layout structure relative to the second direction and in a substantially centered manner on the first linear-shaped interconnect level layout structure relative to the first direction;creating a second rectangular-shaped interlevel connection layout structure to have a horizontal cross-section with a first size as measured in the first direction and a second size as measured in the second direction, the first size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure at least twice the second size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure, and the first size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure larger than a size of the second linear-shaped interconnect level layout structure as measured in the first direction;modifying the layout of the semiconductor device by positioning the second rectangular-shaped interlevel connection layout structure in a substantially centered manner on the second linear-shaped interconnect level layout structure relative to the first direction and in a substantially centered manner on a position located one-half of the gate electrode pitch as measured in the second direction away from the lengthwise-oriented centerline of the first linear-shaped gate electrode level layout structure;creating a third rectangular-shaped interlevel connection layout structure to have a horizontal cross-section with a first size as measured in the first direction and a second size as measured in the second direction, the first size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure at least twice the second size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure, and the first size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure larger than a size of the third linear-shaped interconnect level layout structure as measured in the first direction;modifying the layout of the semiconductor device by positioning the third rectangular-shaped interlevel connection layout structure in a substantially centered manner on the third linear-shaped interconnect level layout structure relative to the first direction and in a substantially centered manner on a position located one-half of the gate electrode pitch as measured in the second direction away from the lengthwise-oriented centerline of the first linear-shaped gate electrode level layout structure, such that the second and third rectangular-shaped interlevel connection layout structures are located on different sides of the first linear-shaped gate electrode level layout structure relative to the second direction; andrecording the layout of the semiconductor device as modified to include each of the first, second, and third rectangular-shaped interlevel connection layout structures on a non-transitory computer readable medium in a format for fabrication of the semiconductor device. 2. The method as recited in claim 1, wherein a smaller of the first and second sizes of the horizontal cross-section of at least one of the first, second, and third rectangular-shaped interlevel connection layout structures is minimally sized within design rule requirements pertaining to a semiconductor chip. 3. The method as recited in claim 1, wherein the first size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure is substantially equal to a minimum transistor channel length allowed by design rule requirements pertaining to a semiconductor chip. 4. The method as recited in claim 1, wherein a larger of the first and second sizes of the horizontal cross-section of at least one of the first, second, and third rectangular-shaped interlevel connection layout structures is larger than a maximum size allowed by design rule for a contact structure. 5. The method as recited in claim 1, wherein the first rectangular-shaped interlevel connection layout structure corresponds to a conductive via structure defined to physically connect to both the first linear-shaped gate electrode level layout structure and the first linear-shaped interconnect level layout structure. 6. The method as recited in claim 5, wherein the second rectangular-shaped interlevel connection layout structure corresponds to a conductive diffusion contact structure defined to physically connect to both the second linear-shaped interconnect level layout structure and a first diffusion region of the first transistor. 7. The method as recited in claim 6, wherein the third rectangular-shaped interlevel connection layout structure corresponds to a conductive diffusion contact structure defined to physically connect to both the third linear-shaped interconnect level layout structure and a second diffusion region of the first transistor. 8. The method as recited in claim 7, wherein the second diffusion region of the first transistor is also a first diffusion region of the second transistor. 9. The method as recited in claim 8, wherein each of the first, second, and third linear-shaped interconnect level layout structures has a respective lengthwise-oriented centerline oriented in the second direction, wherein the lengthwise-oriented centerline of the first linear-shaped interconnect level layout structure is separated from the lengthwise-oriented centerline of the second linear-shaped interconnect level layout structure by an interconnect pitch as measured in the first direction,wherein the lengthwise-oriented centerline of the third linear-shaped interconnect level layout structure is separated from the lengthwise-oriented centerline of the second linear-shaped interconnect level layout structure by the interconnect pitch as measured in the first direction,wherein the second linear-shaped interconnect level layout structure is positioned between the first and second linear-shaped interconnect level layout structures in the first direction. 10. The method as recited in claim 9, wherein the second size of the second rectangular-shaped interlevel connection layout structure is substantially equal to the second size of the third rectangular-shaped interlevel connection layout structure. 11. The method as recited in claim 10, wherein the first size of the first rectangular-shaped interlevel connection layout structure is less than a size of the first linear-shaped interconnect level layout structure as measured in the first direction. 12. The method as recited in claim 11, wherein the first, second, and third rectangular-shaped interlevel connection layout structures are spaced apart from each other in the first direction. 13. The method as recited in claim 12, wherein the first rectangular-shaped interlevel connection layout structure is not positioned directly over the first diffusion region of the first transistor, and wherein the first rectangular-shaped interlevel connection layout structure is not positioned directly over the second diffusion region of the first transistor. 14. The method as recited in claim 13, wherein the first linear-shaped gate electrode level layout structure has at least one end substantially aligned in the first direction with at least one end of the second linear-shaped gate electrode level layout structure. 15. The method as recited in claim 13, wherein the first linear-shaped gate electrode level layout structure has at least one end not aligned in the first direction with at least one end of the second linear-shaped gate electrode level layout structure. 16. The method as recited in claim 1, wherein the first linear-shaped gate electrode level layout structure has at least one end substantially aligned in the first direction with at least one end of the second linear-shaped gate electrode level layout structure. 17. The method as recited in claim 16, wherein each of the first, second, and third linear-shaped interconnect level layout structures has a respective lengthwise-oriented centerline oriented in the second direction, wherein the lengthwise-oriented centerline of the first linear-shaped interconnect level layout structure is separated from the lengthwise-oriented centerline of the second linear-shaped interconnect level layout structure by an interconnect pitch as measured in the first direction,wherein the lengthwise-oriented centerline of the third linear-shaped interconnect level layout structure is separated from the lengthwise-oriented centerline of the second linear-shaped interconnect level layout structure by the interconnect pitch as measured in the first direction,wherein the second linear-shaped interconnect level layout structure is positioned between the first and second linear-shaped interconnect level layout structures in the first direction. 18. The method as recited in claim 17, wherein the first size of the first rectangular-shaped interlevel connection layout structure is less than a size of the first linear-shaped interconnect level layout structure as measured in the first direction. 19. The method as recited in claim 18, wherein the second size of the second rectangular-shaped interlevel connection layout structure is substantially equal to the second size of the third rectangular-shaped interlevel connection layout structure. 20. The method as recited in claim 19, wherein the first, second, and third rectangular-shaped interlevel connection layout structures are spaced apart from each other in the first direction. 21. The method as recited in claim 20, wherein the first linear-shaped gate electrode level layout structure has at least one end not aligned in the first direction with at least one end of the second linear-shaped gate electrode level layout structure. 22. A non-transitory data storage device for storing data to be read by a computer system having program instructions stored thereon for defining an interlevel connection layout structure, comprising: program instructions for identifying a first linear-shaped gate electrode level layout structure that forms a gate electrode of a first transistor and a second linear-shaped gate electrode level layout structure that forms a gate electrode of a second transistor, each of the first and second linear-shaped gate electrode level layout structures oriented to extend lengthwise in a first direction, the first and second linear-shaped gate electrode level layout structures positioned next to each other such that their respective lengthwise-oriented centerlines are separated from each other by a gate electrode pitch as measured in a second direction perpendicular to the first direction;program instructions for identifying a first linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure;program instructions for identifying a second linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure;program instructions for identifying a third linear-shaped interconnect level layout structure that extends lengthwise in the second direction over the first linear-shaped gate electrode level layout structure;program instructions for determining a size of the first linear-shaped gate electrode level layout structure as measured in the second direction;program instructions for calculating a horizontal cross-section of a first rectangular-shaped interlevel connection layout structure to have a first size as measured in the first direction and a second size as measured in the second direction, the second size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure at least twice the first size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure, and the second size of the horizontal cross-section of the first rectangular-shaped interlevel connection layout structure larger than twice the size of the first linear-shaped gate electrode level layout structure as measured in the second direction;program instructions for positioning the first rectangular-shaped interlevel connection layout structure in a substantially centered manner on the first linear-shaped gate electrode level layout structure relative to the second direction and in a substantially centered manner on the first linear-shaped interconnect level layout structure relative to the first direction;program instructions for calculating a horizontal cross-section of a second rectangular-shaped interlevel connection layout structure to have a first size as measured in the first direction and a second size as measured in the second direction, the first size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure at least twice the second size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure, and the first size of the horizontal cross-section of the second rectangular-shaped interlevel connection layout structure larger than a size of the second linear-shaped interconnect level layout structure as measured in the first direction;program instructions for positioning the second rectangular-shaped interlevel connection layout structure in a substantially centered manner on the second linear-shaped interconnect level layout structure relative to the first direction and in a substantially centered manner on a position located one-half of the gate electrode pitch as measured in the second direction away from the lengthwise-oriented centerline of the first linear-shaped gate electrode level layout structure;program instructions for calculating a horizontal cross-section of a third rectangular-shaped interlevel connection layout structure to have a first size as measured in the first direction and a second size as measured in the second direction, the first size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure at least twice the second size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure, and the first size of the horizontal cross-section of the third rectangular-shaped interlevel connection layout structure larger than a size of the third linear-shaped interconnect level layout structure as measured in the first direction;program instructions for positioning the third rectangular-shaped interlevel connection layout structure in a substantially centered manner on the third linear-shaped interconnect level layout structure relative to the first direction and in a substantially centered manner on a position located one-half of the gate electrode pitch as measured in the second direction away from the lengthwise-oriented centerline of the first linear-shaped gate electrode level layout structure, such that the second and third rectangular-shaped interlevel connection layout structures are located on different sides of the first linear-shaped gate electrode level layout structure relative to the second direction; andprogram instructions for recording the horizontal cross-section and position of each of the first, second, and third rectangular-shaped interlevel connection layout structures on a data storage device. 23. The non-transitory data storage device as recited in claim 22, wherein the first rectangular-shaped interlevel connection layout structure corresponds to a conductive via structure defined to physically connect to both the first linear-shaped gate electrode level layout structure and the first linear-shaped interconnect level layout structure. 24. The non-transitory data storage device as recited in claim 23, wherein the second rectangular-shaped interlevel connection layout structure corresponds to a conductive diffusion contact structure defined to physically connect to both the second linear-shaped interconnect level layout structure and a first diffusion region of the first transistor. 25. The non-transitory data storage device as recited in claim 24, wherein the third rectangular-shaped interlevel connection layout structure corresponds to a conductive diffusion contact structure defined to physically connect to both the third linear-shaped interconnect level layout structure and a second diffusion region of the first transistor. 26. The non-transitory data storage device as recited in claim 25, wherein the second diffusion region of the first transistor is also a first diffusion region of the second transistor. 27. The non-transitory data storage device as recited in claim 26, wherein each of the first, second, and third linear-shaped interconnect level layout structures has a respective lengthwise-oriented centerline oriented in the second direction, wherein the lengthwise-oriented centerline of the first linear-shaped interconnect level layout structure is separated from the lengthwise-oriented centerline of the second linear-shaped interconnect level layout structure by an interconnect pitch as measured in the first direction,wherein the lengthwise-oriented centerline of the third linear-shaped interconnect level layout structure is separated from the lengthwise-oriented centerline of the second linear-shaped interconnect level layout structure by the interconnect pitch as measured in the first direction,wherein the second linear-shaped interconnect level layout structure is positioned between the first and second linear-shaped interconnect level layout structures in the first direction. 28. The non-transitory data storage device as recited in claim 27, wherein the second size of the second rectangular-shaped interlevel connection layout structure is substantially equal to the second size of the third rectangular-shaped interlevel connection layout structure. 29. The non-transitory data storage device as recited in claim 28, wherein the first size of the first rectangular-shaped interlevel connection layout structure is less than a size of the first linear-shaped interconnect level layout structure as measured in the first direction. 30. The non-transitory data storage device as recited in claim 29, wherein the first, second, and third rectangular-shaped interlevel connection layout structures are spaced apart from each other in the first direction. 31. The non-transitory data storage device as recited in claim 30, wherein the first rectangular-shaped interlevel connection layout structure is not positioned directly over the first diffusion region of the first transistor, and wherein the first rectangular-shaped interlevel connection layout structure is not positioned directly over the second diffusion region of the first transistor. 32. The non-transitory data storage device as recited in claim 31, wherein the first linear-shaped gate electrode level layout structure has at least one end substantially aligned in the first direction with at least one end of the second linear-shaped gate electrode level layout structure. 33. The non-transitory data storage device as recited in claim 31, wherein the first linear-shaped gate electrode level layout structure has at least one end not aligned in the first direction with at least one end of the second linear-shaped gate electrode level layout structure. 34. The non-transitory data storage device as recited in claim 22, wherein the first linear-shaped gate electrode level layout structure has at least one end substantially aligned in the first direction with at least one end of the second linear-shaped gate electrode level layout structure. 35. The non-transitory data storage device as recited in claim 34, wherein each of the first, second, and third linear-shaped interconnect level layout structures has a respective lengthwise-oriented centerline oriented in the second direction, wherein the lengthwise-oriented centerline of the first linear-shaped interconnect level layout structure is separated from the lengthwise-oriented centerline of the second linear-shaped interconnect level layout structure by an interconnect pitch as measured in the first direction,wherein the lengthwise-oriented centerline of the third linear-shaped interconnect level layout structure is separated from the lengthwise-oriented centerline of the second linear-shaped interconnect level layout structure by the interconnect pitch as measured in the first direction,wherein the second linear-shaped interconnect level layout structure is positioned between the first and second linear-shaped interconnect level layout structures in the first direction. 36. The non-transitory data storage device as recited in claim 35, wherein the first size of the first rectangular-shaped interlevel connection layout structure is less than a size of the first linear-shaped interconnect level layout structure as measured in the first direction. 37. The non-transitory data storage device as recited in claim 36, wherein the second size of the second rectangular-shaped interlevel connection layout structure is substantially equal to the second size of the third rectangular-shaped interlevel connection layout structure. 38. The non-transitory data storage device method as recited in claim 37, wherein the first, second, and third rectangular-shaped interlevel connection layout structures are spaced apart from each other in the first direction. 39. The non-transitory data storage device as recited in claim 38, wherein the first linear-shaped gate electrode level layout structure has at least one end not aligned in the first direction with at least one end of the second linear-shaped gate electrode level layout structure.
Copyright KISTI. All Rights Reserved.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.