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Strained structure of a semiconductor device

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/66
  • H01L-021/02
  • H01L-021/8238
  • H01L-029/78
  • H01L-021/285
  • H01L-029/165
  • H01L-021/768
출원번호 US-0166585 (2014-01-28)
등록번호 US-9236253 (2016-01-12)
발명자 / 주소
  • Chen, Chung-Hsien
  • Ko, Ting-Chu
  • Chang, Chih-Hao
  • Chang, Chih-Sheng
  • Chang, Shou-Zen
  • Wann, Clement Hsingjen
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Slater & Matsil, L.L.P.
인용정보 피인용 횟수 : 0  인용 특허 : 27

초록

A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is di

대표청구항

1. A method comprising: forming a p-type Field Effect Transistor (pFET) on a major surface of a substrate, including:forming a P-gate stack over a P-channel region of the major surface,epitaxially growing a P-strained region in the substrate adjacent to one side of the P-gate stack and extending abo

이 특허에 인용된 특허 (27)

  1. Li,Weimin; Yin,Zhiping, Compositions of matter and barrier layer compositions.
  2. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
  3. Yu Allen S. ; Steffan Paul J., Electroless plated semiconductor vias and channels.
  4. Raaijmakers, Ivo; Werkhoven, Christiaan, In situ dielectric stacks.
  5. Horak, David Vaclav; Koburger, III, Charles William; Mitchell, Peter H.; Nesbit, Larry Alan, Method for manufacturing a multi-level interconnect structure.
  6. Critchlow Dale L. (Burlington VT) DeBrosse John K. (Essex Junction VT) Mohler Rick L. (Williston VT) Noble ; Jr. Wendell P. (Milton VT) Parries Paul C. (Essex Junction VT), Method for providing silicide bridge contact between silicon regions separated by a thin dielectric.
  7. Fiordalice Robert ; Garcia Sam ; Ong T. P., Method of decreasing resistivity in an electrically conductive layer.
  8. Nogami Takeshi ; Dubin Valery ; Cheung Robin, Method of electroplating a copper or copper alloy interconnect.
  9. Sharan, Sujit; Sandhu, Gurtej S.; Gilton, Terry, Method of forming a conductive contact on a substrate and method of processing a semiconductor substrate using an ozone treatment.
  10. Geffken Robert M. ; Luce Stephen E., Method of forming a self-aligned copper diffusion barrier in vias.
  11. Hsu Sheng Teng ; Tweet Douglas James ; Pan Wei ; Evans David Russell, Method of forming amorphous conducting diffusion barriers.
  12. Lin, Jing-Cheng, Method of forming multilayer diffusion barrier for copper interconnections.
  13. Lin, Jing-Cheng, Method of forming multilayer diffusion barrier for copper interconnections.
  14. Hsu Wei-Yung ; Hong Qi-Zhong, Method of improving texture of metal films in semiconductor integrated circuits.
  15. Sandhu, Gurtej S.; Doan, Trung Tri; Rhodes, Howard E.; Sharan, Sujit; Ireland, Philip J.; Roberts, Martin Ceredig, Methods of forming conductive interconnects.
  16. Danek Michal ; Levy Karl B., Multilayer diffusion barriers.
  17. Nishioka, Naho; Tsuji, Naoki, Nonvolatile semiconductor memory device with peripheral circuit part comprising at least one of two transistors having lower conductive layer same perpendicular structure as a floating gate.
  18. Adetutu Olubunmi Olufemi ; Denning Dean J. ; Hayden James D. ; Subramanian Chitra K. ; Sitaram Arkalgud R., Process for forming a semiconductor device.
  19. Liu, Chung-Shi; Yu, Chen-Hua, Semiconductor contact barrier.
  20. Nguyen Bich-Yen ; Olowolafe J. Olufemi ; Maiti Bikas ; Adetutu Olubunmi ; Tobin Philip J., Semiconductor device having a metal containing layer overlying a gate dielectric.
  21. Nakajima Kazuaki,JPX ; Akasaka Yasushi,JPX ; Miyano Kiyotaka,JPX ; Suguro Kyoichi,JPX, Semiconductor device with conductive oxidation preventing film and method for manufacturing the same.
  22. Koyama Mitsutoshi,JPX ; Kubota Takeshi,JPX, Semiconductor device with pure copper wirings and method of manufacturing a semiconductor device with pure copper wiring.
  23. Li, Weimin; Yin, Zhiping, Semiconductor devices, and semiconductor processing methods.
  24. Pelella, Mario M.; Sinha, Shankar; Chan, Simon S., Silicide MOSFET architecture and method of manufacture.
  25. Beyer, Sven; Press, Patrick; Feudel, Thomas, Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor.
  26. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
  27. Nogami Takeshi ; Dubin Valery M., Via with barrier layer for impeding diffusion of conductive material from via into insulator.
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