A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is di
A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.
대표청구항▼
1. A method comprising: forming a p-type Field Effect Transistor (pFET) on a major surface of a substrate, including:forming a P-gate stack over a P-channel region of the major surface,epitaxially growing a P-strained region in the substrate adjacent to one side of the P-gate stack and extending abo
1. A method comprising: forming a p-type Field Effect Transistor (pFET) on a major surface of a substrate, including:forming a P-gate stack over a P-channel region of the major surface,epitaxially growing a P-strained region in the substrate adjacent to one side of the P-gate stack and extending above the major surface, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, forming a first P-silicide region on the P-strained region, andforming a second P-silicide region on the P-strained region after forming the first P-silicide region, the second P-silicide region being formed under the first P-silicide region, wherein the first and second P-silicide regions are collectively a first distance from the P-channel region and collectively impart a first strain on the P-channel region;forming an n-type Field Effect Transistor (nFET) including:forming an N-gate stack over a N-channel region of the major surface,epitaxially growing an N-strained region in the substrate adjacent to one side of the N-gate stack and having a top surface below the top surface of the P-strained region, wherein a lattice constant of the N-strained region is different from the lattice constant of the substrate and different from the lattice constant of the P-strained region, andforming a first N-silicide region on the N-strained region, and forming a second N-silicide region on the N-strained region after forming the first N-silicide region, the second N-silicide region being formed under the first N-silicide region, wherein the first and second N-silicide regions are collectively a second distance from the N-channel region and collectively impart a second strain on the N-channel region, the second distance being less than the first distance and the second strain being greater than the first strain by virtue of the second distance being less than the first distance. 2. The method of claim 1, further comprising: depositing a first metal layer over the P-strained region and the N-strained region;reacting at least some of the first metal layer with the P-strained region and with the N-strained region to form a first P-silicide region and a first N-silicide region, respectively;removing unreacted first metal layer;depositing an dielectric layer over the first P-silicide region and the first N-silicide region;patterning the dielectric layer to expose at least a portion of the first P-silicide region and least a portion of the first N-silicide region;depositing a second metal layer on the exposed portion of first P-silicide region and the exposed portion of the first N-silicide region;reacting at least some of the second metal layer with the P-strained region and with the N-strained region to form a second P-silicide region and a second N-silicide region, respectively; andremoving unreacted second metal layer. 3. The method of claim 2, wherein the step of reacting at least some of the first metal layer with the P-strained region and with the N-strained region comprises performing a rapid thermal anneal process. 4. The method of claim 3, further comprising performing a second rapid thermal anneal process to convert the first P-silicide region and the first N-silicide region, respectively, from a high resistance state to a low resistance state. 5. The method of claim 1, wherein the first N-silicide region and the second N-silicide region impart a tensile strain on an N-channel region of the substrate. 6. The method of claim 2, wherein the second metal layer penetrates through the first P-silicide region and the first N-silicide region, respectively, to react with the P-strained region and the N-strained region, respectively, to form the second P-silicide region and the second N-silicide region, respectively. 7. The method of claim 2, wherein the step of removing unreacted first metal layer comprises exposing the unreacted first metal layer to a solution of NH4OH, H2O2, and deionized water. 8. A method comprising: forming a strained P-region adjacent a P-channel region of a substrate and a strained N-region adjacent an N-channel region of the substrate, the strained P-region extending above a top surface of the substrate and the strained N-region being co-planar with the top surface of the substrate;depositing a first metal layer on the strained P-region and the strained N-region simultaneously;reacting the first metal layer with the strained P-region and the strained N-region to form a first P-silicide region and a first N-silicide region simultaneously;depositing a second metal layer on the first P-silicide region and the first N-silicide region simultaneously; andreacting the second metal layer with the strained P-region and the strained N-region to form a second P-silicide region and a second N-silicide region simultaneously, wherein the first and second N-silicide regions impart greater strain on the N-channel region than strain imparted on the P-channel region by the first and second P-silicide regions by virtue of the first and second N-silicide regions being closer to the N-channel region than the first and second P-silicide regions are to the P-channel region. 9. The method of claim 8, further comprising removing unreacted first metal layer after forming the first P-silicide region and the first N-silicide region, and removing unreacted second metal layer after forming the second P-silicide region and the second N-silicide region. 10. The method of claim 8, further comprising performing a thermal anneal on the second metal layer and the strained P-region and N-strained region, such that the second metal layer penetrates the first P-Silicide region and the first N-silicide region, respectively, to react with the strained P-region and strained N-region, respectively. 11. The method of claim 8, wherein the step of forming a strained P-region adjacent a P-channel region and a strained N-region adjacent an N-channel region comprises epitaxially growing a first material having a first lattice constant to have a top surface above a top surface of a substrate in which the strained P-region is formed, and epitaxially growing a second material having a second lattice constant different than the first lattice constant to have a top surface below the top surface of the substrate. 12. A method comprising: forming a p-type Field Effect Transistor (pFET) on a major surface of a substrate, including:forming a P-gate stack over a P-channel region of the major surface,etching a recess into the major surface adjacent to one side of the P-gate stack;epitaxially growing a P-strained region in the recess and extending above the major surface, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate,forming a first P-silicide region on the P-strained region, andforming a second P-silicide region on the P-strained region after forming the first P-silicide region, the second P-silicide region extending under the first P-silicide region, wherein the first and second P-silicide regions are a first distance from the P-channel region;forming an n-type Field Effect Transistor (pFET) on the major surface of a substrate, including:forming a N-gate stack over a N-channel region of the major surface,etching a recess into the major surface adjacent to one side of the N-gate stack;epitaxially growing a N-strained region in the recess and extending above the major surface, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate and the lattice constant of the P-strained region,forming a first N-silicide region on the N-strained region, andforming a second N-silicide region on the N-strained region after forming the first N-silicide region, the second N-silicide region extending under the first N-silicide region, wherein the first and second N-silicide regions are a second first distance from the N-channel region, and wherein the first and second N-silicide regions impart greater strain on the N-channel region than strain imparted on the P-channel region by the first and second P-silicide regions by virtue of the first and second N-silicide regions being closer to the N-channel region than the first and second P-silicide regions are to the P-channel region. 13. The method of claim 12, wherein a top surface of the N-strained region is coplanar with the major surface of the substrate. 14. The method of claim 12, further comprising: depositing a first metal layer over the P-strained region and the N-strained region;reacting at least some of the first metal layer with the P-strained region and with the N-strained region to form a first P-silicide region and a first N-silicide region, respectively;removing unreacted first metal layer;depositing an dielectric layer over the first P-silicide region and the first N-silicide region;patterning the dielectric layer to expose at least a portion of the first P-silicide region and least a portion of the first N-silicide region;depositing a second metal layer on the exposed portion of first P-silicide region and the exposed portion of the first N-silicide region;reacting at least some of the second metal layer with the P-strained region and with the N-strained region to form a second P-silicide region and a second N-silicide region, respectively; andremoving unreacted second metal layer. 15. The method of claim 12, wherein the first P-silicide region and the first N-silicide region are formed simultaneously. 16. The method of claim 12, wherein the first P-silicide region and the second P-silicide region are formed on both sides of the P-gate stack. 17. The method of claim 16, the first N-silicide region and the second N-silicide region are formed on both sides of the N-gate stack. 18. The method of claim 14, further comprising removing unreacted first metal layer after forming the first P-silicide region and the first N-silicide region, and removing unreacted second metal layer after forming the second P-silicide region and the second N-silicide region. 19. The method of claim 18, further comprising performing a thermal anneal on the second metal layer and the P-strained region and N-strained region, such that the second metal layer penetrates the first P-Silicide region and the first N-silicide region, respectively, to react with the P-strained region and N-strained region, respectively.
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