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A circuit for driving a gate of a power MOS transistor includes an adaptive pull-up unit and an adaptive pull-down unit. The adaptive pull-up unit is connected between a first power source voltage and the gate of the power MOS transistor. The adaptive pull-up unit maximizes pull-up current driving a

A circuit for driving a gate of a power MOS transistor includes an adaptive pull-up unit and an adaptive pull-down unit. The adaptive pull-up unit is connected between a first power source voltage and the gate of the power MOS transistor. The adaptive pull-up unit maximizes pull-up current driving ability. The adaptive pull-down unit is connected between a second power source voltage and the gate of the power MOS transistor. The adaptive pull-down unit maximizes pull-down current driving ability.

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1. A circuit for driving a gate of a power metal oxide semiconductor MOS transistor, the circuit comprising: an adaptive pull-up unit connected between a first power source voltage and the gate of the power MOS transistor, the adaptive pull-up unit configured to maximize pull-up current driving abil

1. A circuit for driving a gate of a power metal oxide semiconductor MOS transistor, the circuit comprising: an adaptive pull-up unit connected between a first power source voltage and the gate of the power MOS transistor, the adaptive pull-up unit configured to maximize pull-up current driving ability when a drain-source voltage of the power MOS transistor falls equal to or less than a threshold voltage of the power MOS transistor while a falling transition slope of the power MOS transistor is being driven in a multistage scheme by increasing the pull-up current driving ability stepwisely in response to a leading edge of a gate driving pulse; andan adaptive pull-down unit connected between a second power source voltage and the gate of the power MOS transistor, the adaptive pull-down unit configured to maximize pull-down current driving ability when a gate source voltage of the power MOS transistor falls equal to or less than the threshold voltage of the power MOS transistor while a rising transition slope of the power MOS transistor is being driven in a multistage scheme by increasing the pull-down current driving ability stepwisely in response to a trailing edge of the gate driving pulse. 2. The circuit of claim 1, wherein the adaptive pull-up unit comprises a plurality of pull-up transistors connected in parallel between the first power source voltage and the gate of the power MOS transistor; a drain-source voltage detecting unit configured to detect whether a level of the drain-source voltage of the power MOS transistor falls equal to or less than the threshold voltage of the power MOS transistor;a pull-up driving signal generating unit configured to generate a plurality of pull-up driving signals to drive the pull-up transistors stepwisely in response to the leading edge of the gate driving pulse; anda gate unit configured to drive a pull-up transistor of a last stage from among the pull-up transistors selectively in response to a pull-up driving signal of the last stage from among the pull-up driving signals and a detection signal from the drain source voltage detecting unit. 3. The circuit of claim 2, wherein the drain source voltage detecting unit comprises: a first MOS transistor that has a gate coupled to the first power source voltage and a drain coupled to a drain of the power MOS transistor;a second MOS transistor that has a gate coupled to the source of the first MOS transistor and a source coupled to the second power source voltage;a first current source connected between the first power source voltage and a drain of the second MOS transistor; anda CMOS inverter that outputs a drain voltage of the second MOS transistor as the detection signal of a CMOS level. 4. The circuit of claim 3, wherein the first and second MOS transistors comprise Lateral Double Diffuse LD MOS transistors that have a threshold voltage equal to a threshold voltage of the power MOS transistor. 5. The circuit of claim 1, wherein the adaptive pull-down unit comprises: a plurality of pull-down transistors connected in parallel between the second power source voltage and the gate of the power MOS transistor;a gate-source voltage detecting unit configured to detect whether a level of a gate-source voltage of the power MOS transistor is between a Miller Plateau voltage level of the power MOS transistor and a level of the threshold voltage;a pull-down driving signal generating unit configured to generate a plurality of pull-down driving signals for driving the pull-down transistors step by step in response to the trailing edge of the gate driving pulse; anda gate unit configured to mask a pull-down driving signal of a last stage among the pull-down driving signals such that the pull-down driving signal is prevented from being applied to a pull-down transistor of the last stage among the pull-down transistors unless the gate source voltage of the power MOS transistor falls equal to or less than the threshold voltage of the power MOS transistor in response to the detection signal of the gate-source voltage detecting unit. 6. The circuit of claim 5, wherein the gate-source voltage detecting unit comprises: a first voltage comparing unit configured to detect whether the gate source voltage of the power MOS transistor falls equal to or less than a first preset voltage;a second voltage comparing unit configured to detect whether the gate source voltage of the power MOS transistor falls equal to or less than the threshold voltage; anda masking signal generating unit configured to generate a masking control signal by combining outputs of the first and second voltage comparing units with each other. 7. The circuit of claim 6, wherein the first voltage comparing unit comprises: a first MOS transistor that has a gate coupled to the gate of the power MOS transistor;a first current source connected between the first power source voltage and a drain of the first MOS transistor;a second MOS transistor that has a gate and a drain coupled to a source of the first MOS transistor and a source coupled to the second power source voltage;a third MOS transistor that has a gate coupled to the drain of the first MOS transistor and a source coupled to the first power source voltage;a second current source connected between a drain of the third MOS transistor and the second power source voltage; anda CMOS inverter that outputs a drain voltage of the second MOS transistor as the detection signal of a CMOS level. 8. The circuit of claim 7, wherein the second voltage comparing unit comprises: a fourth MOS transistor that has a gate coupled to the gate of the power MOS transistor;a third current source connected between the first power source voltage and a drain of the fourth MOS transistor;a fifth MOS transistor that has a gate coupled to the drain of the fourth MOS transistor and a source coupled to the first power source voltage; anda fourth current source connected between a drain of the fifth MOS transistor and the second power source voltage. 9. The circuit of claim 8, wherein the masking signal generating unit comprises an XOR gate to which an output of the CMOS inverter of the first voltage detecting unit and a drain output of the fifth MOS transistor of the second voltage comparing unit are input. 10. The circuit of claim 8, wherein the first and fourth MOS transistors comprise LD MOS transistors that have a threshold voltage equal to the threshold voltage of the power MOS transistor. 11. A circuit for driving a gate of a power metal oxide semiconductor MOS transistor, the circuit comprising: a pair of pull-up transistors connected in parallel between a first power source voltage and the gate of the power MOS transistor;a pair of pull-down transistors connected in parallel between a second power source voltage and the gate of the power MOS transistor;a drain-source voltage detecting unit configured to detect whether a level of a drain source voltage of the power MOS transistor falls equal to or less than the threshold voltage of the power MOS transistor;a gate-source voltage detecting unit configured to detect whether a level of a gate source voltage of the power MOS transistor is between a Miller Plateau voltage level of the power MOS transistor and a level of the threshold voltage;a driving signal generating unit configured to generate a pair of pull-up and pull-down driving signals to drive the pair of pull-up and pull-down transistors step by step according to a gate driving pulse;a pull-up gate unit configured to drive one of the pair of pull-up transistors, which is turned on later than a remaining pull-up transistor, selectively in response to one of the pair of pull-up driving signals being activated later than a remaining pull-up driving signal and a detection signal of the drain source voltage detecting unit; anda pull-down gate unit configured to mask one of the pair of the pull-down driving signals activated later than a remaining pull-down driving signal such that the pull-down driving signal is prevented from being applied to one of the pair of the pull-down transistors turned on later than a remaining pull-down transistor unless the gate source voltage of the power MOS transistor falls equal to or less than the threshold voltage of the power MOS transistor in response to a detection signal of the gate source voltage detecting unit. 12. The circuit of claim 11, wherein the driving signal generating unit comprises: an input latch configured to generate a first output and a second output, in which the first output is subject to a falling transition after the second output is primarily subject to the falling transition and the pull-down transistors are turned off in response to a rising transition of the gate driving pulse, and the second output is subject to the rising transition after the first output is primarily subject to the rising transition and the pull-up transistors are turned off in response to the falling transition of the gate driving pulse;a pull-up latch configured to generate a first output and a second output, in which the second output of the pull-up latch is subject to the falling transition prior to the first output of the pull-up latch when the falling transition occurs and the first output of the pull-up latch is subject to the rising transition prior to the second output of the pull-up latch when the rising transition occurs in response to the first output of the input latch; anda pull-down latch configured to generate a first output and a second output, in which the second output of the pull-down latch is subject to the falling transition prior to the first output of the pull-down latch when the falling transition occurs and the first output of the pull-down latch is subject to the rising transition prior to the second output of the pull-down latch when the rising transition occurs in response to the second output of the input latch,wherein the second output of the pull-up latch is provided as a gate driving signal for one of the pair of the pull-up transistors,wherein the first output of the pull-up latch is provided through the pull-up gate unit as a gate driving signal for a remaining one of the pull-up transistors,wherein the first output of the pull-down latch is provided as a gate driving signal for one of the pair of the pull-down transistors, andwherein the second output of the pull-down latch is provided as a gate driving signal for a remaining one of the pull-down transistors. 13. The circuit of claim 12, wherein the pull-up gate unit comprises an OR gate, and the pull-down gate unit comprises an AND gate. 14. A DC-DC converter comprising a power metal oxide semiconductor MOS transistor, the converter comprising: a pair of pull-up transistors connected in parallel between a first power source voltage and a gate of the power MOS transistor;a pair of pull-down transistors connected in parallel between a second power source voltage and the gate of the power MOS transistor;a drain-source voltage detecting unit configured to detect whether a level of a drain source voltage of the power MOS transistor falls equal to or less than the threshold voltage of the power MOS transistor;a gate-source voltage detecting unit configured to detect whether a level of a gate source voltage of the power MOS transistor is between a Miller Plateau voltage level of the power MOS transistor and a level of the threshold voltage;a circuit configured to provide first though fourth signals according to a gate driving pulse;a first logic gate configured to receive an output of the drain-source voltage detecting unit and the first signal as input and provide an output to a gate of one of the pull-up transistors;a first buffer configured to provide the second signal to a gate of the other pull-up transistor;a second buffer configured to provide the third signal to a gate of one of the pull-down transistors; anda second logic gate configured to receive an output of the gate-source voltage detecting unit and the fourth signal as input and provide and output to a gate of the other pull-down transistor. 15. The DC-DC converter of claim 14, further comprising: a first capacitor connected between a DC input voltage and the second power source voltage;an inductor connected between the first capacitor and a drain of the power MOS transistor;a diode connected between the inductor and the drain of the power MOS transistor; anda second capacitor connected between the diode and the second power source voltage,wherein an output node between the diode and the second capacitor outputs a DC output voltage. 16. The DC-DC converter of claim 14, wherein the first signal is provided to a last one of the pull-up transistors, and the fourth signal is provided to a last one of the pull-down transistors. 17. The DC-DC converter of claim 14, wherein the first logic gate is an OR gate and the second logic gate is an AND gate. 18. The DC-DC converter of claim 14, wherein the circuit comprises: a first OR gate configured to receive a signal based on the gate driving pulse;a second OR gate configured to receive an output of the first OR gate and provide an output to the first logic gate; anda first AND gate configured to receive an output of the first OR gate and provide an output to the first buffer. 19. The DC-DC converter of claim 18, wherein the circuit further comprises: a second AND gate configured to receive the signal based on the gate driving pulse;a third OR gate configured to receive an output of the second AND gate and providing an output to the second buffer; anda third AND gate configured to receive an output of the second AND gate and provide an output to the second logic gate. 20. The DC-DC converter of claim 19, wherein an output of the second OR gate is provided to an input of the first AND gate, an output of the first AND gate is provided to an input of the second OR gate, wherein an output of the third OR gate is provided to an input of the third AND gate, and an output of the third AND gate is provided to an input of the third OR gate.