A system and method for frequency diversity uses interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes. Subcarriers of one or more interlaces are interleaved in a bit reversal fashion and the one or more interlaces are inte
A system and method for frequency diversity uses interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes. Subcarriers of one or more interlaces are interleaved in a bit reversal fashion and the one or more interlaces are interleaved in the bit reversal fashion.
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1. A method for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: in a processor:interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcar
1. A method for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: in a processor:interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; andinterleaving the one or more interlaces such that the mapped symbols are interleaved into a second order. 2. The method of claim 1, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. 3. The method of claim 2, wherein said interleaving subcarriers comprises: creating an empty subcarrier index vector (SCIV);initializing an index variable (i) to zero;converting i to its bit reversed nine-bit value (ibr);appending ibr into the SCIV, if ibr is less than 511; andincrementing i by one and repeat the converting, appending and incrementing, if is less than 511. 4. The method of claim 1, wherein the interleaving subcarriers of one or more interlaces in a bit reversal fashion involves mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table. 5. The method of claim 1, wherein the interleaving the one or more interlaces occurs every OFDM symbol. 6. An apparatus for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: a processor configured to interleave subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; anda processor configured to interleave the one or more interlaces in the bit reversal fashion such that the mapped symbols are interleaved into a second order. 7. The apparatus of claim 6, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. 8. The apparatus of claim 6, wherein the number of interlaces is eight. 9. The apparatus of claim 6, wherein the processor configured to interleave subcarriers of one or more interlaces in a bit reversal fashion is further configured to map symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table. 10. The apparatus of claim 6, wherein the interleaving the one or more interlaces occurs every OFDM symbol. 11. A processor executing instructions in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, the instructions comprising: interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; andinterleaving the one or more interlaces in the bit reversal fashion such that the mapped symbols are interleaved into a second order. 12. The processor of claim 11, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. 13. The processor of claim 11, wherein the number of interlaces is eight. 14. The processor of claim 11, wherein the interleaving subcarriers of one or more interlaces in a bit reversal fashion involves mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table. 15. The processor of claim 11, wherein the interleaving the one or more interlaces occurs every OFDM symbol. 16. An apparatus for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: means for interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; andmeans for interleaving the one or more interlaces in the bit reversal fashion such that the mapped symbols are interleaved into a second order. 17. The apparatus of claim 16, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. 18. The apparatus of claim 16, wherein the number of interlaces is eight. 19. The apparatus of claim 16, wherein the means for interleaving subcarriers of one or more interlaces in a bit reversal fashion comprises means for mapping symbols of a constellation symbol sequence into corresponding subcarriers in a sequential linear fashion according to an assigned slot index using an interlace table. 20. The apparatus of claim 16, wherein the means for interleaving the one or more interlaces occurs every OFDM symbol. 21. A system for interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes, comprising: a processor configured to interleaving subcarriers of one or more interlaces in a bit reversal fashion such that mapped symbols of corresponding subcarriers are interleaved into a first order; anda processor configured to interleave the one or more interlaces in the bit reversal fashion such that the mapped symbols are interleaved into a second order. 22. The system of claim 21, wherein the bit reversal fashion is a reduce-set bit reversal operation if the number of subcarriers is not a power of two. 23. The system of claim 22, wherein said processor configured to interleave subcarriers is further configured to: create an empty subcarrier index vector (SCIV);initialize an index variable (i) to zero;convert i to its bit reversed nine-bit value (ibr);append ibr into the SCIV, if ibr is less than 511; andincrement i by one and repeat the converting, appending and incrementing, if i is less than 511. 24. The system of claim 21, wherein the processor configured to interleave the one or more interlaces is further configured to: for a 1K FFT size, map interlaces in four consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i {0, 1, . . . 499}, to a jth subcarrier of interlace Ik(s), whereink=BR2(SCIV[i] mod 4),j=floor(SCIV[i]/4), andBR2(*) is a bit reversal operation for two bits. 25. The system of claim 21, wherein the processor configured to interleave the one or more interlaces is further configured to: for a 2K FFT size, map interlaces in 2 consecutive OFDM symbols to slot s by mapping an ith modulation symbol, where i {0, 1, . . . 499}, to a jth subcarrier of interlace Ik(s), whereink=(SCIV[i] mod 2), andj=floor(SCIV[i]/2).
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