A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a
A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.
대표청구항▼
1. A system, the system comprising: a processing system comprising a plurality processors; andat least one separated cache not part of any processor;a bus system connecting the processing system to one or more external devices;at least one interface transmitting data between the processing system an
1. A system, the system comprising: a processing system comprising a plurality processors; andat least one separated cache not part of any processor;a bus system connecting the processing system to one or more external devices;at least one interface transmitting data between the processing system and external devices via the bus system;at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and whereinthe at least one interface to transmit data via the bus system using a protocol, comprising: i. the module ID of an interface, a processor, a separated cache requesting a transmission,ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/oriii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a transmission; and wherein the module ID is defined by a configuration unit. 2. The system of claim 1, further including multiplexers responsive to module IDs. 3. The system of claim 2, further including decoders connected to the multiplexors, the decoders being responsive to both the module IDs of a target and to addresses within a target. 4. A system, the system comprising: a processing system comprising a plurality of processors; andat least one separated cache not part any processor;a bus system connecting the processing system to one or more external devices;at least one interface transmitting data between the processing system and external devices via the bus system;at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and whereinthe at least one interface to transmit data via the bus system using a protocol, comprising: i. the module ID of an interface, a processor, a separated cache requesting a transmission,ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/oriii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a train mission; and wherein the at least one separated cache comprises a separated cache segment for at least some of the plurality of processors; the system further comprising: an interconnect system interconnecting each of the separated cache segments with each of the processors, each of the processors with neighboring processors, and each of the separated cache segments with neighboring separated cache segments; andan arbiter, the arbiter controlling access of a processor to the interconnect system. 5. The bus system of claim 4 where the arbiter is operable to allow processor access in chronological sequence. 6. A system, the system comprising: a processing system comprising a plurality of processors; andat least one separated cache not part of any processor;a bus system connecting the processing system to one or more external devices;at least one interface transmitting data between the processing system and external devices via the bus system;at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and whereinthe at least one interface to transmit data via the bus system using a protocol, comprising: i. the module ID of an interface, a processor, a separate cache requesting a transmission,ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/oriii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a transmission; and wherein the at least one interface comprises a buffer memory; the buffer memory having three associated pointers: i. a first pointer to point to the buffer location from which data is output from the buffer;ii. a second pointer to point the buffer location to which data is input to the buffer; andiii. a third pointer to store the value of the first pointer at the start of a data transfer; wherein the at least one interface is to i. store transfer data in the buffer memory;ii. transmit data to a selected to one of said external devices;iii. receive from the selected one of said external devices transmitting information as to whether a data transfer was successful or has failed;iv. if the information indicates that a data transfer has failed, repeat the data transfer from buffer position indicated by the third pointer. 7. A system, the system comprising: a processing system comprising a plurality of processors; andat least one separated cache not part of any processor;a bus system connecting the processing system to one or more external devices;at least one interface transmitting data between the processing system and external devices via the bus system;at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and whereinthe at least one interface to transmit data via the bus system using a protocol, comprising: i. the module ID of an interface, a processor, a separate cache requesting a transmission,ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/oriii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a transmission; and wherein said at least one interface is to store and transmit data to external devices in packets via a buffer memory. 8. A system, the system comprising: a processing system comprising a plurality of processors; andat least one separated cache not part of any processor;a bus system connecting the processing system to one or more external devices;at least one interface transmitting data between the processing system an external devices via the bus system;at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and whereinthe at least one interface to transmit data via the bus system using a protocol comprising: i. the module ID of an interface, a processor, a separated cache requesting a transmission,ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/oriii. the address of a target within the interface, the processor, the separated cache or the eternal device unit receiving a transmission; and wherein the at least one interface is further to generate time stamps that are transmitted with data transfers. 9. The system according to claim 8, wherein the time stamps are unique. 10. A system, the system comprising: a processing system comprising a plurality of processors; andat least one separated cache not part of any processor;a bus system connecting the processing system to one or more external devices;at least one interface transmitting data between the processing system and external devices via the bus system;at least some of the plurality of processors, the at least one interface, and the at least one separated cache having a module identification (ID); and whereinthe at least one interface to transmit data via the bus system using a protocol, comprising: i. the module ID of an interface, a processor, a separated cache requesting a transmission,ii. the module ID of an interface, a processor, a separated cache receiving a transmission; and/oriii. the address of a target within the interface, the processor, the separated cache or the external device unit receiving a transmission; and wherein the bus system is operable to transmit interrupt requests.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (193)
Shyr, Jin-sheng, Adaptive scheduling of function cells in dynamic reconfigurable logic.
Chin Danny (West Windsor Township NJ) Peters ; Jr. Joseph E. (East Brunswick NJ) Taylor ; Jr. Herbert H. (Hopewell Township NJ), Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to inc.
Robinson Jeffrey I. (New Fairfield CT) Rouse Keith (Lebanon NJ) Krassowski Andrew J. (Long Valley NJ) Montlick Terry F. (Bethlehem CT), Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tas.
Pechanek Gerald G. (Cary NC) Larsen Larry D. (Raleigh NC) Glossner Clair John (Durham NC) Vassiliaadis Stamatis (Zoetermeer NLX), Array processor communication architecture with broadcast processor instructions.
Wang,Albert Ren Rui; Ruddell,Richard; Goodwin,David William; Killian,Earl A.; Bhattacharyya,Nupur; Medina,Marines Puig; Lichtenstein,Walter David; Konas,Pavlos; Srinivasan,Rangarajan; Songer,Christop, Automated processor generation system for designing a configurable processor and method for the same.
Goetting F. Erich (Cupertino CA) Parlour David B. (Pittsburgh PA) Trimberger Stephen M. (San Jose CA), Compact logic cell for field programmable gate array chip.
Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.
Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
Sluijter Robert J. (Eindhoven NLX) Huizer Cornelis M. (Eindhoven NLX) Dijkstra Hendrik (Eindhoven CA NLX) Slavenburg Gerrit A. (Sunnyvale CA), Data processing module and video processing system incorporating same.
Sutherland Jim (Sunnyvale CA) Popli Sanjay (Sunnyvale CA) Alturi Venkata (Sunnyvale CA) Furtek Frederick (Menlo Park CA), Diagonal wiring between abutting logic cells in a configurable logic array.
Angle Richard L. ; Harriman ; Jr. Edward S. ; Ladwig Geoffrey B., Distributed pipeline memory architecture for a computer system with even and odd pids.
Pechanek Gerald G. ; Larsen Larry D. ; Glossner Clair John ; Vassiliaadis Stamatis,NLX, Distributed processing array with component processors performing customized interpretation of instructions.
DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
Hartmann Alfred C., Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip.
Hiller John (New York NY) Johnsen Howard (Granite Spring NY) Mason John (Ramsey NJ) Mulhearn Brian (Paterson NJ) Petzinger John (Oakland NJ) Rosal Joseph (Bronx NY) Satta John (White Plains NY) Shurk, Highly parallel computer architecture employing crossbar switch with selectable pipeline delay.
Shams Soheil ; Shu David B., Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same.
Takano, Hiroyuki, Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions.
Evan Shabtai (Saratoga CA) Sander Wendell B. (Los Gatos CA), Input/output section for an intelligent cell which provides sensing, bidirectional communications and control.
Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Jennings ; III Earle W. (Richardson TX) Landers George H. (Mountain View CA), Logic system of logic networks with programmable selected functions and programmable operational controls.
Van Doren Stephen R. ; Steely ; Jr. Simon C. ; Gharachorloo Kourosh ; Sharma Madhumitra, Mechanism for optimizing generation of commit-signals in a distributed shared-memory system.
Steely ; Jr. Simon C. ; Sharma Madhumitra ; Van Doren Stephen R. ; Gharachorloo Kourosh, Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches.
Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple cont.
Kundu Aniruddha ; Khandekar Narendra, Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic.
Razdan Rahul ; Webb ; Jr. David Arthur James ; Keller James ; Meyer Derrick R. ; Leibholz Daniel Lawrence, Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol.
Sharma Madhumitra ; Van Doren Stephen R. ; Gharachorloo Kourosh ; Steely ; Jr. Simon C., Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system.
Borkenhagen John Michael ; Eickemeyer Richard James ; Flynn William Thomas ; Wottreng Andrew Henry, Method and apparatus to force a thread switch in a multithreaded processor.
Kahle James A. ; Mallick Soummya ; McDonald Robert G., Method and system for constructing a program including out-of-order threads and processor and method for executing threa.
Jones Michael B. ; Leach Paul J. ; Draves ; Jr. Richard P. ; Barrera ; III Joseph S. ; Levi Steven P. ; Rashid Richard F. ; Fitzgerald Robert P., Method and system for scheduling the execution of threads using optional time-specific scheduling constraints.
Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
Cooke, Laurence H.; Phillips, Christopher E.; Wong, Dale, Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic.
Dean Jeffrey A. ; Waldspurger Carl A., Method for estimating statistics of properties of memory system interactions among contexts in a computer system.
Ekanadham Kattamuri ; Moreira Jose Eduardo ; Naik Vijay Krishnarao, Method for resource control in parallel environments using program organization and run-time support.
Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD).
Bruce Richard H. (Los Altos CA) Gastinel Jean (Palo Alto CA) Gunning William F. (Los Altos Hills CA) Overton Michael (Palo Alto CA), Multi-segmented bus and method of operation.
Arimilli, Ravi Kumar; Dodson, John Steven; Guthrie, Guy Lynn, Multiprocessor computer system with sectored cache line mechanism for cache intervention.
Takahashi Hajime,JPX ; Hattori Nobuhisa,JPX ; Tsuzuki Toshihide,JPX ; Funaki Jun,JPX, Multiprocessor system connected by a duplicated system bus having a bus status notification line.
Holsztynski Wlodzimierz (Mountainview CA) Benton Richard W. (Altamonte Springs FL) Johnson W. Keith (Goleta CA) McNamara Robert A. (Orlando FL) Naeyaert Roger S. (Plano TX) Noden Douglas A. (Orlando , Parallel data processor.
Hillis W. Daniel (Brookline MA), Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and.
Butts Michael R. (Portland OR) Batcheller Jon A. (Newburg OR), Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logi.
Bertolet Allan Robert (Williston VT) Ferguson Kenneth (Edinburgh GB6) Gould Scott Whitney (South Burlington VT) Millham Eric Ernest (St. George VT) Palmer Ronald Raymond (Westford VT) Worth Brian (Mi, Programmable array I/O-routing resource.
Gould Scott Whitney (South Burlington VT) Furtek Frederick Curtis (Menlo Park CA) Keyser ; III Frank Ray (Colchester VT) Worth Brian A. (Milton VT) Zittritsch Terrance John (Williston VT), Programmable array clock/reset resource.
Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array.
Bertolet Allan Robert (Williston VT) Clinton Kim P. N. (Essex Junction VT) Fuller Christine Marie (Williston VT) Gould Scott Whitney (South Burlington VT) Hartman Steven Paul (Jericho VT) Iadanza Jos, Programmable logic cell having configurable gates and multiplexers.
Jefferson David E. ; McClintock Cameron ; Schleicher James ; Lee Andy L. ; Mejia Manuel ; Pedersen Bruce B. ; Lane Christopher F. ; Cliff Richard G. ; Reddy Srinivas T., Programmable logic device architecture with super-regions having logic regions and a memory region.
Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device with hierarchical confiquration and state storage.
John K. Gee ; David A. Greve ; David S. Hardin ; Allen P. Mass ; Michael H. Masters ; Nick M. Mykris ; Matthew M. Wilding, Real time processor capable of concurrently running multiple independent JAVA machines.
Hung, Ching-Yu; Estevez, Leonardo W.; Rabadi, Wissam A., Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing).
Barker Thomas N. (Vestal NY) Collins Clive A. (Poughkeepsie NY) Dapp Michael C. (Endwell NY) Dieffenderfer James W. (Owego NY) Lesmeister Donald M. (Vestal NY) Nier Richard E. (Apalachin NY) Retter E, SIMD/MIMD processing memory element (PME).
MacWilliams Peter D. (Aloha OR) Rasmussen Norman J. (Hillsboro OR) Wade Nicholas D. (Vancouver WA) Wu William S. F. (Cupertino CA), Scalable cache attributes for an input/output bus.
Michael Ignatowski ; Thomas James Heller, Jr. ; Gottfried Andreas Goldiran DE, Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls.
Pechanek Gerald G. (Cary NC) Larsen Larry D. (Raleigh NC) Glossner Clair John (Durham NC) Vassiliaadis Stamatis (Zoetermeer NLX) McCabe Daniel H. (Chapel Hill NC), Selective processing and routing of results among processors controlled by decoding instructions using mask value derive.
Larson Ronald J. (Minneapolis MN), State machine having a variable timing mechanism for varying the duration of logical output states of the state machine.
Rubinstein Jon (Palo Alto CA) Klingman Kenneth C. (Portola CA), System for assigning interrupts to least busy processor that already loaded same class of interrupt routines.
Webb Charles Franklin ; Bair Dean G. ; Farrell Mark Steven ; Krumm Barry Watson ; Mak Pak-kin ; Navarro Jennifer Almoradie ; Slegel Timothy John, System serialization with early release of individual processor.
Sluijter Robert J. (Eindhoven NLX) Huizer Cornelis M. (Eindhoven NLX) Dijkstra Hendrik (Eindhoven NLX), System with plurality of processing elememts each generates respective instruction based upon portions of individual wor.
Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
Garverick Tim (Cupertino CA) Sutherland Jim (Sunnyvale CA) Popli Sanjay (Sunnyvale CA) Alturi Venkata (Sunnyvale CA) Smith ; Jr. Arthur (San Carlos CA) Pickett Scott (Los Gatos CA) Hawley David (Belm, Versatile and efficient cell-to-local bus interface in a configurable logic array.
Schmidt Ulrich (Freiburg DEX) Caesar Knut (Gundelfingen DEX), Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.