초록 ▼

Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern

Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.

대표청구항 ▼

1. A method for determining overlay accuracy in a semiconductor device, said method comprising: forming a lower semiconductor pattern of a semiconductor material bounded laterally by a dielectric, said lower semiconductor pattern including a first resistor structure and a separate second resistor st

1. A method for determining overlay accuracy in a semiconductor device, said method comprising: forming a lower semiconductor pattern of a semiconductor material bounded laterally by a dielectric, said lower semiconductor pattern including a first resistor structure and a separate second resistor structure formed of the same material layer and physically separated from said first resistor structure;forming an overlying pattern in a further material layer or layers, disposed over said lower semiconductor pattern;siliciding exposed portions of said first resistor structure and said second resistor structure not covered by said overlying pattern;measuring a first resistance of said first resistor structure and measuring a second resistance of said second resistor structure; andcalculating overlay accuracy between said overlying pattern and said lower semiconductor pattern based on said first resistance and said second resistance. 2. The method as in claim 1, wherein said forming a lower semiconductor pattern includes forming said first resistor structure and said second resistor structure in at least one test portion and forming active device structures in active device portions of a semiconductor device, on a semiconductor substrate, and said forming an overlying pattern includes forming portions in said at least one test portion and in said active device portions. 3. The method as in claim 1, wherein said forming an overlying pattern comprises depositing said further material layer or layers, forming a photolithographic pattern over said further material layer or layers, then etching, said etching exposing said exposed portions of said first resistor structure and said second resistor structure, and wherein said further material layer or layers blocks silicidation of covered portions of said lower semiconductor pattern including said first resistor structure and said second resistor structure. 4. The method as in claim 1, wherein said lower semiconductor pattern comprises an active area pattern, said semiconductor material comprising a silicon surface of a semiconductor substrate and said dielectric comprises a field oxide. 5. The method as in claim 1, wherein said lower semiconductor pattern comprises a polysilicon pattern. 6. The method as in claim 1, wherein said lower semiconductor pattern includes each of said first and second resistor structures having a plurality of parallel leads having different lengths and coupled to one another by orthogonal leads. 7. The method as in claim 6, wherein said parallel leads of said first resistor structure are parallel to said parallel leads of said second resistor structure, longer ones of said parallel leads of said first resistor structure extend closer to said second resistor structure than shorter ones of said parallel leads of said first resistor structure, and said first resistor structure includes said parallel leads having respective lengths that increase progressively along a first orthogonal direction and said second resistor structure includes said parallel leads having respective lengths that decrease progressively along said first orthogonal direction. 8. The method as in claim 6, wherein, for each of said first and second resistor structures, each of said parallel leads includes one end that terminates at the same perpendicular location and an opposed end joined to an adjacent one of said parallel leads, by one said orthogonal lead, said opposed ends and said orthogonal leads forming a step-like structure in each of said first and second resistor structures. 9. A method for determining overlay accuracy in a semiconductor device, said method comprising: forming a lower semiconductor pattern of a semiconductor material bounded laterally by a dielectric, said lower semiconductor pattern including a first resistor structure and a separate second resistor structure formed of the same material layer;forming an overlying pattern in a further material layer or layers, disposed over said lower semiconductor pattern;siliciding exposed portions of said first resistor structure and said second resistor structure not covered by said overlying pattern;measuring a first resistance of said first resistor structure and measuring a second resistance of said second resistor structure; andcalculating overlay accuracy between said overlying pattern and said lower semiconductor pattern based on said first resistance and said second resistance,wherein each of said first resistor structure and said second resistor structure comprises a zigzag portion including transverse leads disposed orthogonal to a direction from said first resistor structure to said second resistor structure, said transverse leads including first transverse leads of said first resistor structure spaced at different distances from said second resistor structure, and second transverse leads of said second resistor structure spaced at different distances from said first resistor structure. 10. The method as in claim 9, wherein said forming a lower semiconductor pattern further includes forming a third resistor structure and a fourth resistor structure, each of said third resistor structure and said fourth resistor structure including a zigzag portion with further transverse leads extending orthogonal to a direction from said third resistor structure to said fourth resistor structure and disposed orthogonal to said transverse leads;further comprising measuring a third resistance of said third resistor structure and measuring a fourth resistance of said fourth resistor structure; andwherein said calculating overlay accuracy is further based on said third resistance and said fourth resistance and includes calculating alignment accuracy in the orthogonal directions. 11. The method as in claim 10, wherein said forming a lower semiconductor pattern includes forming a group of said first resistor structure, said second resistor structure, said third resistor structure and said fourth resistor structure on multiple locations of a semiconductor substrate. 12. The method as in claim 11, wherein said transverse leads include first transverse leads of said first resistor structure spaced at different distances from said second resistor structure, second transverse leads of said second resistor structure spaced at different distances from said first resistor structure, third transverse leads of said third resistor structure spaced at different distances from said fourth resistor structure, and fourth transverse leads of said fourth resistor structure spaced at different distances from said third resistor structure. 13. A method for determining overlay accuracy in a semiconductor device, said method comprising: forming a lower semiconductor pattern of a silicon material bounded laterally by a dielectric, said lower semiconductor pattern including at least a resistor structure;forming a first overlying pattern in a first material layer or layers, over said semiconductor pattern;forming a second overlying pattern in a second material layer or layers, over said semiconductor pattern;siliciding exposed portions of said lower semiconductor pattern not covered by said first overlying pattern or said second overlying pattern;measuring a resistance of only said resistor structure, said resistor structure electrically isolated from said first and second overlying patterns; andcalculating alignment accuracy between said first overlying pattern and said second overlying pattern based on said resistance,wherein said exposed portions comprise a gap between boundaries of said first overlying pattern and said second overlying pattern. 14. The method as in claim 13, wherein said lower semiconductor pattern includes a plurality of parallel leads of different lengths and orthogonal leads coupling ends of each said parallel lead to an adjacent one of said parallel leads. 15. A method for determining overlay accuracy in a semiconductor device, said method comprising: forming a lower semiconductor pattern of a semiconductor material bounded by a dielectric, said lower semiconductor pattern including a first resistor structure and a second resistor structure;forming an overlying pattern in a material layer or layers, over said lower semiconductor pattern;siliciding exposed portions of said first resistor structure and said second resistor structure not covered by said overlying pattern;measuring a first resistance of said first resistor structure and measuring a second resistance of said second resistor structure; andcalculating overlay accuracy between said overlying pattern and said lower semiconductor pattern based on said first resistance and said second resistance, wherein each of said first resistor structure and said second resistor structure comprises a zig-zag portion including transverse leads disposed orthogonal to a direction from said first resistor structure to said second resistor structure. 16. The method as in claim 1, wherein said lower semiconductor pattern includes each of said first and second resistor structures having a plurality of parallel leads having different lengths and coupled to one another by orthogonal leads and said calculating includes establishing a correlation between a number of said orthogonal leads that were silicided during said siliciding and said first and second resistances. 17. A method for determining overlay accuracy in a semiconductor device, said method comprising: forming a first pattern of a silicon material on a first device level;siliciding all portions of said first pattern not covered by at least a further pattern formed at further device levels and electrically isolated from, and not directly contacting, said first pattern;determining a measured resistance by measuring resistance of only said first pattern after said siliciding; andestablishing a correlation between said measured resistance and overlay accuracy of said at least a further pattern,wherein said at least a further pattern comprises a duality of further patterns formed of different material layers in two different device levels. 18. The method as in claim 17, wherein said overlay accuracy is an overlay accuracy between said duality of further patterns. 19. The method as in claim 17, wherein said overlay accuracy is an overlay accuracy between said at least a further pattern and said first pattern. 20. The method as in claim 13, wherein said first overlying pattern and said second overlying pattern are each formed of materials that include a lower dielectric layer such that said lower semiconductor pattern first pattern is not electrically connected to first overlying pattern and said second overlying pattern.