초록 ▼

A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined e

A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.

대표청구항 ▼

1. A method performable by a processor including an accumulator, the method comprising: selecting at least one event, thereby producing at least one selected event;generating a reset signal to the accumulator responsive to said at least one selected event;responsive to said reset signal, resetting t

1. A method performable by a processor including an accumulator, the method comprising: selecting at least one event, thereby producing at least one selected event;generating a reset signal to the accumulator responsive to said at least one selected event;responsive to said reset signal, resetting the accumulator to zero or an initial value while avoiding breaking pipelined execution of the processor; andstoring said at least one event in an event register; wherein said selecting said at least one event is performed by:logically ANDing a first input from said event register with a second input from an event selection register thereby producing a first AND output including a first plurality of outputs, andlogically ORing together the first plurality of outputs, thereby producing a first OR output, wherein said generating a reset signal to the accumulator is responsive to said first OR output. 2. The method of claim 1, further comprising: generating said at least one event by an address generation unit (AGU) operatively attached to the processor. 3. The method of claim 1, further comprising: storing said first OR output in a shift register;logically ANDing an output from said shift register with an output of a stage selection register, thereby producing a second AND output, wherein said second AND output includes a second plurality of outputs; wherein said stage selection register specifies a number of cycles after an event occurs for performing said resetting;logically ORing together said second plurality of outputs, thereby producing a second OR output; and said generating said reset signal to the accumulator responsive to said second OR output. 4. The method of claim 1, further comprising: inputting a plurality of image patches by an address generation unit (AGU) operatively attached to the processor;calculating memory addresses for said image patches by the address generation unit (AGU);initiating a processing loop for processing by the processor said image patches; andduring said processing, generating said at least one event responsive to said memory addresses;while processing said processing loop, said resetting the accumulator of the processor responsive to said at least one selected event. 5. The method of claim 4, further comprising: specifying a number of cycles after said at least one selected event; and said generating said reset of said accumulator after said specified number of cycles. 6. The method of claim 4 further comprising: after said at least one selected event, specifying a first number of cycles and a second number of cycles; andsaid generating resets of said accumulator after said specified first number and second number of cycles. 7. A system comprising: a processor including an accumulator;logical circuitry configured to select at least one event to produce at least one selected event, to generate a reset signal to the accumulator responsive to said at least one selected event; and responsive to said reset signal, to reset the accumulator to zero or an initial value while avoiding breaking pipelined execution of the processor;an event register configured to store said at least one event;an event selection register;a logical AND gate having a first input from said event register, a second input from said event selection register and a first AND output including a first plurality of outputs, anda logical OR gate operable to logically OR together the first plurality of outputs, to produce a first OR output, wherein said reset signal to the accumulator is generated responsive to said first OR output. 8. The system of claim 7, further comprising: an address generation unit (AGU) operatively attached to the processor; wherein the events are generated by said address generation unit (AGU). 9. The system of claim 7, further comprising: a first address generation unit and a second address generation unit each configured to generate events;said logical circuitry being a first logical circuitry configured to receive the events generated by the first and second address generation units;a second logical circuitry configured to receive the events generated by the first and second address generation units;a first accumulator operatively connected to said first logical circuitry; anda second accumulator operatively connected to said second logical circuitry; wherein responsive to said events, the first logical circuitry resets the first accumulator and the second logical circuitry resets the second accumulator. 10. The system of claim 7, further comprising: a shift register configured to store said first OR output;a stage selection register; wherein an output from said shift register is logically ANDed with an output of said stage selection register to produce thereby a second AND output,wherein said second AND output includes a second plurality of outputs; wherein said stage selection register specifies a number of cycles after an event occurs to reset the accumulator;a logical OR gate operable to logically OR together said second plurality of outputs, to produce thereby a second OR output; andgenerate said reset signal to the accumulator responsive to said second OR output. 11. The system of claim 10, wherein said shift register includes bits which are shiftable to enable a history of instruction cycles to be kept. 12. The system of claim 10, wherein said stage selection register is used by a software of said processor to specify at least one number of cycles after an event generated by said AGU happens to generate a reset of said accumulator. 13. The system of claim 10, wherein said second OR output is a single bit output. 14. The system of claim 10, wherein said first OR output is a single bit output.