Selective coupling of an address line to an element bank of a vector register file
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-012/00
G06F-009/30
출원번호
US-0654730
(2012-10-18)
등록번호
US-9268571
(2016-02-23)
발명자
/ 주소
Ingle, Ajay Anant
Hoffman, Marc M.
Mathew, Deepak
출원인 / 주소
QUALCOMM Incorporated
대리인 / 주소
Kamarchik, Peter Michael
인용정보
피인용 횟수 :
0인용 특허 :
13
초록▼
A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessi
A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.
대표청구항▼
1. An apparatus comprising: a vector register file including a plurality of hardware element banks;a plurality of sets of address lines, each set of address lines of the plurality of sets of address lines including: a first address line configured to receive a first address, anda second address line
1. An apparatus comprising: a vector register file including a plurality of hardware element banks;a plurality of sets of address lines, each set of address lines of the plurality of sets of address lines including: a first address line configured to receive a first address, anda second address line configured to receive a second address;a plurality of address line selectors, wherein each address line selector of the plurality of address line selectors is coupled to a corresponding set of address lines of the plurality of sets of address lines and is configured to generate an output by selecting the first address line or the second address line of the set of address lines coupled to the address line selector; anda single read port configured to access data stored within the plurality of hardware element banks,wherein each hardware element bank of the plurality of hardware element banks is configured to be selectively addressed by one of the first address or the second address, andwherein a first hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a first output of a first address line selector, to a particular first address line of a first set of address lines coupled to the first address line selector. 2. The apparatus of claim 1, wherein the first set of address lines comprises the particular first address line and a particular second address line coupled to the first address line selector, wherein a second set of address lines comprises a third address line coupled to a second address line selector and a fourth address line coupled to the second address line selector, wherein each of the particular first address line and the particular second address line is configured to be selectively coupled, via the first output of the first address line selector, to the first hardware element bank, and wherein each of the third address line and the fourth address line is configured to be selectively coupled, via a second output of the second address line selector, to a second hardware element bank of the plurality of hardware element banks. 3. The apparatus of claim 1, wherein the plurality of address line selectors comprises a plurality of multiplexers, and wherein a number of multiplexers of the plurality of multiplexers corresponds to a number of hardware element banks of the plurality of hardware element banks. 4. The apparatus of claim 3, wherein a particular multiplexer of the plurality of multiplexers is coupled to a particular hardware element bank of the plurality of hardware element banks, wherein a plurality of data lines couple the plurality of hardware element banks to the single read port, and wherein: each hardware element bank of the plurality of hardware element banks is coupled to the single read port via a separate data line of the plurality of data lines. 5. The apparatus of claim 1, wherein the first set of address lines includes the particular first address line and a particular second address line, wherein a second set of address lines includes a third address line and a fourth address line, and wherein: the first hardware element bank is configured to be selectively addressed by one of the particular first address line or the particular second address line, anda second hardware element bank of the plurality of hardware element banks is configured to be selectively addressed by one of the third address line or the fourth address line. 6. The apparatus of claim 1, wherein the plurality of address line selectors comprises a plurality of multiplexers, further comprising a plurality of connections coupling the plurality of hardware element banks to the plurality of multiplexers, wherein the plurality of multiplexers is connected to a common data selector, and wherein: the common data selector is configured to receive a selection pattern corresponding to each hardware element bank of the plurality of hardware element banks. 7. The apparatus of claim 1, further comprising a single write port configured to store data within each hardware element bank of the plurality of hardware element banks, wherein the vector register file is integrated in a processor, and wherein the processor, during a single instruction, is configured to: instruct the single read port to access the data as read data;modify the read data; andinstruct the single write port to update the vector register file with the modified read data. 8. A method comprising: selectively coupling address lines of a plurality of sets of address lines to a plurality of hardware element banks of a vector register file using a plurality of address line selectors, wherein: each set of address lines of the plurality of sets of address lines includes: a first address line configured to receive a first address, anda second address line configured to receive a second address,each address line selector of the plurality of address line selectors is coupled to a corresponding set of address lines of the plurality of sets of address lines and is configured to generate an output by selecting the first address line or the second address line of the set of address lines coupled to the address line selector,the first address line of a first set of address lines of the plurality of sets of address lines and the second address line of the first set of address lines are selectively coupled to a first hardware element bank of the plurality of hardware element banks,the first address line of the first set of address lines and the second address line of the first set of address lines are selectively coupled according to a selection pattern, andthe vector register file is coupled to a single read port;coupling the first address line of the first set of address lines to the first hardware element bank according to a particular selection pattern;selectively addressing the first hardware element bank using the first address line of the first set of address lines; andaccessing data stored within the first hardware element bank via the single read port. 9. The method of claim 8, further comprising: coupling the first address line of a second set of address lines of the plurality of sets of address lines to a second hardware element bank of the plurality of hardware element banks according to the selection pattern, wherein the first hardware element bank and the second hardware element bank are coupled to a common address line. 10. The method of claim 8, further comprising: coupling the second address line of a second set of address lines of the plurality of sets of address lines to a second hardware element bank of the plurality of hardware element banks according to the selection pattern, wherein the first hardware element bank and the second hardware element bank are coupled to different address lines. 11. An apparatus comprising: means for storing vector data, the means for storing vector data coupled to a single read port and including a plurality of hardware element banks;means for selectively coupling address lines of a plurality of sets of address lines to the plurality of hardware element banks, each set of address lines of the plurality of sets of address lines including a first address line configured to receive a first address and a second address line configured to receive a second address, the means for selectively coupling including: a plurality of address line selectors, wherein each address line selector of the plurality of address line selectors is coupled to a corresponding set of address lines of the plurality of sets of address lines and is configured to generate an output by selecting the first address line or the second address line of the set of address lines coupled to the address line selector; andmeans for accessing, via the single read port, data stored within the plurality of hardware element banks,wherein each hardware element bank of the plurality of hardware element banks is configured to be selectively addressed by one of the first address or the second address,wherein a first hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a first output of a first address line selector, to the first address line of a first set of address lines of the plurality of sets of address lines, the first set of address lines coupled to the first address line selector, andwherein a second hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a second output of a second address line selector, to the second address line of a second set of address lines of the plurality of sets of address lines, the second set of address lines coupled to the second address line selector. 12. The apparatus of claim 11, wherein the means for selectively coupling is responsive to a selection pattern. 13. A non-transitory computer readable storage medium comprising processor-executable instructions that, when executed by a processor, cause the processor to: generate a selection pattern to selectively couple address lines of a plurality of sets of address lines to a plurality of hardware element banks of a vector register file using a plurality of address line selectors, wherein: each set of address lines of the plurality of sets of address lines includes: a first address line configured to receive a first address, anda second address line configured to receive a second address,each address line selector of the plurality of address line selectors is coupled to a corresponding set of address lines of the plurality of sets of address lines and is configured to generate an output by selecting the first address line or the second address line of the set of address lines coupled to the address line selector, andthe vector register file is coupled to a single read port; andaccess data stored within the plurality of hardware element banks, wherein: each hardware element bank of the plurality of hardware element banks is configured to be selectively addressed by one of the first address or the second address via the single read port,a first hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a first output of a first address line selector, to the first address line of a first set of address lines of the plurality of sets of address lines, the first set of address lines coupled to the first address line selector, anda second hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a second output of a second address line selector, to the second address line of a second set of address lines of the plurality of sets of address lines, the second set of address lines coupled to the second address line selector. 14. The non-transitory computer readable storage medium of claim 13, wherein particular first address lines of the plurality of sets of address lines and particular second address lines of the plurality of sets of address lines are configured to be selectively coupled to the plurality of hardware element banks through respective multiplexers of a plurality of multiplexers. 15. An apparatus comprising: a vector register file including a plurality of hardware element banks;a plurality of sets of address lines, each set of address lines of the plurality of sets of address lines including: a first address line configured to receive a first address, anda second address line configured to receive a second address;a plurality of address line selectors, wherein each address line selector of the plurality of address line selectors is coupled to a corresponding set of address lines of the plurality of sets of address lines and is configured to generate an output by selecting the first address line or the second address line of the set of address lines coupled to the address line selector; anda single write port configured to store data within the plurality of hardware element banks,wherein each hardware element bank of the plurality of hardware element banks is configured to be selectively addressed by one of the first address or the second address, andwherein a first hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a first output of a first address line selector, to the first address line of a first set of address lines coupled to the first address line selector. 16. The apparatus of claim 15, wherein the vector register file includes a plurality of vector registers, and wherein: each vector register of the plurality of vector registers is accessible by instructions that reference a respective vector register name. 17. The apparatus of claim 15, wherein two adjacent hardware element banks of the plurality of hardware element banks are selectively coupled to two second address lines of two corresponding sets of address lines of the plurality of sets of address lines. 18. The apparatus of claim 15, further comprising a single read port configured to access data stored within each hardware element bank of the plurality of hardware element banks, wherein the vector register file is integrated in a processor, and wherein the processor, during execution of a single instruction, is configured to: instruct the single read port to access the data as read data;modify the read data; andinstruct the single write port to update the vector register file with the modified read data. 19. The apparatus of claim 15, wherein a particular hardware element bank of the plurality of hardware element banks is coupled to a multiplexer of a plurality of multiplexers configured to receive a control to select one of the first address line or the second address line of the first set of address lines, and wherein the particular hardware element bank has a write data line. 20. The apparatus of claim 19, wherein: the plurality of multiplexers is connected to a common data selector, andthe common data selector is configured to receive a selection pattern corresponding to each hardware element bank of the plurality of hardware element banks. 21. A method comprising: selectively coupling address lines of a plurality of sets of address lines to a plurality of hardware element banks of a vector register file using a plurality of address line selectors, wherein: each set of address lines of the plurality of sets of address lines includes: a first address line configured to receive a first address, anda second address line configured to receive a second address,each address line selector of the plurality of address line selectors is coupled to a corresponding set of address lines of the plurality of sets of address lines and is configured to generate an output by selecting the first address line or the second address line of the set of address lines coupled to the address line selector,the first address line of a first set of address lines of the plurality of sets of address lines and the second address line of the first set of address lines are selectively coupled to a first hardware element bank of the plurality of hardware element banks, andthe vector register file is coupled to a single write port;coupling the first address line of the first set of address lines to the first hardware element bank according to a particular selection pattern;selectively addressing the first hardware element bank using the first address line of the first set of address lines; andstoring data within the first hardware element bank via the single write port. 22. The method of claim 21, further comprising: coupling the first address line of a second set of address lines of the plurality of sets of address lines to a second hardware element bank of the plurality of hardware element banks according to the particular selection pattern, wherein the first hardware element bank and the second hardware element bank are coupled to a common address line. 23. The method of claim 21, further comprising: coupling the second address line of a second set of address lines of the plurality of sets of address lines to a second hardware element bank of the plurality of hardware element banks according to the particular selection pattern, wherein the first hardware element bank and the second hardware element bank are coupled to different address lines. 24. An apparatus comprising: means for storing vector data, the means for storing vector data coupled to a single write port and including a plurality of hardware element banks;means for selectively coupling address lines of a plurality of sets of address lines to the plurality of hardware element banks, each set of address lines of the plurality of sets of address lines including a first address line configured to receive a first address and a second address line configured to receive a second address, the means for selectively coupling including: a plurality of address line selectors, wherein each address line selector of the plurality of address line selectors is coupled to a corresponding set of address lines of the plurality of sets of address lines and is configured to generate an output by selecting the first address line or the second address line of the set of address lines coupled to the address line selector; andmeans for writing, via the single write port, data within the plurality of hardware element banks,wherein each hardware element bank of the plurality of hardware element banks is configured to be selectively addressed by one of the first address or the second address,wherein a first hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a first output of a first address line selector, to the first address line of a first set of address lines of the plurality of sets of address lines, the first set of address lines coupled to the first address line selector, andwherein a second hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a second output of a second address line selector, to the second address line of a second set of address lines of the plurality of sets of address lines, the second set of address lines coupled to the second address line selector. 25. The apparatus of claim 24, wherein the means for selectively coupling is responsive to a selection pattern. 26. A non-transitory computer readable storage medium comprising processor-executable instructions that, when executed by a processor, cause the processor to: generate a selection pattern to selectively couple address lines of a plurality of sets of address lines to a plurality of hardware element banks of a vector register file using a plurality of address line selectors, wherein: each set of address lines of the plurality of sets of address lines includes: a first address line configured to receive a first address, anda second address line configured to receive a second address,each address line selector of the plurality of address line selectors is coupled to a corresponding set of address lines of the plurality of sets of address lines and is configured to generate an output by selecting the first address line or the second address line of the set of address lines coupled to the address line selector, andthe vector register file is coupled to a single write port; andstore data within the plurality of hardware element banks, wherein: each hardware element bank of the plurality of hardware element banks is configured to be selectively addressed by one of the first address or the second address via the single write port,a first hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a first output of a first address line selector, to the first address line of a first set of address lines of the plurality of sets of address lines, the first set of address lines coupled to the first address line selector, anda second hardware element bank of the plurality of hardware element banks is configured to be selectively coupled, via a second output of a second address line selector, to the second address line of a second set of address lines of the plurality of sets of address lines, the second set of address lines coupled to the second address line selector. 27. The non-transitory computer readable storage medium of claim 26, wherein particular first address lines of the plurality of sets of address lines and particular second address lines of the plurality of sets of address lines are configured to be selectively coupled to the plurality of hardware element banks through respective multiplexers of a plurality of multiplexers. 28. The apparatus of claim 1, wherein all of the hardware element banks of the plurality of hardware element banks are configured to be selectively addressed according to a selection pattern. 29. The apparatus of claim 1, wherein the plurality of address line selectors comprises a plurality of multiplexers, wherein each multiplexer of the plurality of multiplexers is configured to selectively couple a set of address lines of the plurality of sets of address lines to a respective hardware element bank of the plurality of hardware element banks, and wherein all of the hardware element banks of the plurality of hardware element banks are selectively addressed, via the plurality of multiplexers, based on a selection pattern. 30. The apparatus of claim 1, wherein the first address line selector comprises a first multiplexer, and wherein inputs of the first multiplexer are coupled to corresponding address lines of the first set of address lines. 31. The method of claim 8, further comprising selectively addressing all of the hardware element banks of the plurality of hardware element banks according to the particular selection pattern. 32. The apparatus of claim 15, wherein all of the hardware element banks of the plurality of hardware element banks are configured to be selectively addressed according to a selection pattern. 33. The method of claim 21, further comprising selectively addressing all of the hardware element banks of the plurality of hardware element banks according to the particular selection pattern.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (13)
Gostin Gary B. ; Barr Matthew F. ; McGuffey Ruth A. ; Roan Russell L., Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems.
Parameswar, Akilesh; Fiske, James Alexander Stuart; Gonzalez, Ricardo E., System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes.
Sakai Kenichi (Yokohama JPX) Sakamoto Kazushi (Kawasaki JPX) Nakatani Shoji (Kawasaki JPX), Vector data processing apparatus wherein a time slot for access to a bank of vector registors is assigned based on memor.
Kashiyama Masamori (Hadano JPX) Ishii Koichi (Hadano JPX) Kawabe Shun (Machida JPX) Usami Masami (Ome JPX), Vector processor performing data operations in one half of a total time period of write operation and the read operation.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.