Method for manufacturing a semiconductor on insulator structure having low electrical losses
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-027/12
H01L-021/762
H01L-029/06
출원번호
US-0612772
(2015-02-03)
등록번호
US-9293473
(2016-03-22)
우선권정보
FR-09 58658 (2009-12-04)
발명자
/ 주소
Reynaud, Patrick
Kerdiles, Sebastien
Delprat, Daniel
출원인 / 주소
SOITEC
대리인 / 주소
TraskBritt
인용정보
피인용 횟수 :
0인용 특허 :
15
초록▼
A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the
A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.
대표청구항▼
1. A semiconductor-on-insulator (SeOI) structure comprising a support substrate made of silicon, an oxide layer, and a thin layer of semiconductor material, wherein: a polycrystalline silicon layer is interleaved between the support substrate and the oxide layer, the polycrystalline silicon layer ha
1. A semiconductor-on-insulator (SeOI) structure comprising a support substrate made of silicon, an oxide layer, and a thin layer of semiconductor material, wherein: a polycrystalline silicon layer is interleaved between the support substrate and the oxide layer, the polycrystalline silicon layer having a resistivity that is greater than 5,000 Ω·cm; anda semiconductive decoupling layer is disposed on the support substrate and between the support substrate and the polycrystalline silicon layer, the semiconductor decoupling layer having a mesh parameter different form a mesh parameter of the support substrate. 2. The SeOI structure of claim 1, wherein the polycrystalline silicon layer has an average resistivity that is greater than 10,000 Ohms·cm. 3. The SeOI structure of claim 2, wherein the polycrystalline silicon layer has an average resistivity that is greater than 50,000 Ohms·cm. 4. The SeOI structure of claim 1, wherein the resistivity of the support substrate is greater than 1,000 Ω·cm. 5. The SeOI structure of claim 1, wherein the resistivity of the support substrate is greater than 2,000 Ω·cm. 6. The SeOI structure of claim 1, wherein the resistivity of the support substrate is greater than 3,000 Ω·cm. 7. The SeOI structure of claim 1, wherein the support substrate comprises monocrystalline silicon. 8. The SeOI structure of claim 1, wherein the decoupling layer comprises polycrystalline silicon. 9. The SeOI structure of claim 8, wherein the semiconductive decoupling layer also contains another atomic species-based semiconductor material. 10. The SeOI structure of claim 1, wherein the semiconductive decoupling layer is SiC or SiGe. 11. The SeOI structure of claim 1, further comprising another decoupling layer between the polycrystalline silicon layer and the thin layer of semiconductor material. 12. The SeOI structure of claim 11, further comprising at least one layer stack constituting at least one additional polycrystalline silicon layer and at least one additional decoupling layer between the another decoupling layer and the thin layer of semiconductor material. 13. The SeOI structure of claim 1, wherein the support substrate has a resistivity that is greater than 1,000 Ω·cm and the polycrystalline silicon layer has a resistivity that is greater than 10,000 Ohm s·cm. 14. The SeOI structure of claim 1, wherein the semiconductive decoupling layer contains polycrystalline silicon and another atomic species-based semiconductor material. 15. The SeOI structure of claim 1, wherein the oxide layer comprises silicon dioxide. 16. The SeOI structure of claim 1, wherein the mesh parameter of the semiconductive decoupling layer differs from the mesh parameter of the support substrate by greater than 5%. 17. A semiconductor-on-insulator (SeOI) structure comprising a monocrystalline silicon support substrate, an oxide layer, and a thin layer of semiconductor material, wherein: a decoupling layer is disposed on a surface of the support substrate, the decoupling layer comprising a polycrystalline material including silicon and having a mesh parameter different from a mesh parameter of the support substrate;a polycrystalline silicon layer is disposed on the decoupling layer on a side thereof opposite the support substrate, the polycrystalline silicon layer having a resistivity that is greater than 5,000 Ohms·cm;the oxide layer is disposed over the polycrystalline silicon layer on a side thereof opposite the support substrate; andthe thin layer of semiconductor material is disposed over the oxide layer on a side thereof opposite the support substrate. 18. The SeOI structure of claim 17, wherein the decoupling layer includes another atomic species-based species in addition to silicon. 19. The SeOI structure of claim 18, wherein the decoupling layer comprises SiC or SiGe.
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이 특허에 인용된 특허 (15)
Watanabe Tokujiro (Tokyo JPX), Capacitor built-in semiconductor integrated circuit and process of fabrication thereof.
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