Device for generating an adjustable bandgap reference voltage with large power supply rejection rate
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G05F-001/625
G05F-003/30
출원번호
US-0616481
(2015-02-06)
등록번호
US-9298202
(2016-03-29)
우선권정보
FR-11 54266 (2011-05-17)
발명자
/ 주소
Fort, Jimmy
Soude, Thierry
출원인 / 주소
STMICROELECTRONICS (ROUSSET) SAS
대리인 / 주소
Slater & Matsil, L.L.P.
인용정보
피인용 횟수 :
0인용 특허 :
10
초록▼
An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages acros
An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages across the terminals, where the first amplifier has a first stage that is biased by the current inversely proportional to absolute temperature and is arranged according to a folded setup with first PMOS transistors arranged according to a common-gate setup. The first circuit also includes a feedback stage with an input connected to the first amplifier output. The feedback stage output is connected to the first stage input and to a terminal of the core. The second circuit includes a follower amplifier connected to a terminal of the core and separated from the first amplifier and the output module is connected to the feedback stage.
대표청구항▼
1. A circuit comprising: a core comprising a first terminal and a second terminal and configured to generate a current proportional to absolute temperature when voltages across the first and second terminals of the core are equalized;a first amplifier comprising a first stage that includes a first P
1. A circuit comprising: a core comprising a first terminal and a second terminal and configured to generate a current proportional to absolute temperature when voltages across the first and second terminals of the core are equalized;a first amplifier comprising a first stage that includes a first PMOS transistor coupled to the first terminal and a second PMOS transistor coupled to the second terminal;a follower amplifier coupled to a terminal of the core and configured to generate a current inversely proportional to absolute temperature, wherein the follower amplifier is separated from the first amplifier;a feedback stage comprising a first transistor coupled to the first terminal and having a first input gate and a second transistor coupled to the second terminal and having a second input gate, wherein an output of the first stage of the first amplifier is coupled to the first and second input gates; andan output module configured to generate a reference signal based on a reference current proportional to a sum of the current proportional to absolute temperature and the current inversely proportional to absolute temperature. 2. The circuit according to claim 1, wherein the first amplifier is a differential-input single-output amplifier and the feedback stage is a single-input differential-output feedback stage. 3. The circuit according to claim 1, further comprising a bias loop coupled to the first amplifier and the follower amplifier, wherein the bias loop is configured to bias the first amplifier based on the current inversely proportional to absolute temperature. 4. The circuit of claim 3, further comprising a first inverter stage arranged in a common-source setup and coupled between the first amplifier and the feedback stage. 5. The circuit according to claim 3, wherein the follower amplifier comprises a second amplifier and a feedback transistor having a gate coupled to an output of the second amplifier,the bias loop comprises a first additional transistor having a gate connected with a gate of the feedback transistor and configured to generate a current copy of the feedback transistor; andfurther comprising a first resistive circuit, wherein the feedback transistor and the first resistive circuit are coupled in series between a power supply terminal and a reference terminal. 6. The circuit according to claim 5, further comprising a plurality of gate connected NMOS bias transistors coupled to the first additional transistor, the first amplifier, and the follower amplifier, wherein the plurality of gate connected NMOS bias transistors are configured to cause a flow of a bias current in the first additional transistor, the first amplifier, and the follower amplifier, the bias current equal to the current inversely proportional to absolute temperature or to a fraction of the current inversely proportional to absolute temperature. 7. The circuit according to claim 5, wherein the first stage of the first amplifier comprises a differential pair of branches connected between the first terminal and the second terminal of the core and the reference terminal. 8. The circuit according to claim 5, further comprising: a first auxiliary transistor forming with the first additional transistor a first cascode setup;an output PMOS transistor included in the output module; andat least one second auxiliary transistor forming with the output PMOS transistor a second cascode setup. 9. The circuit according to claim 3, wherein the first transistor of the feedback stage comprises a PMOS transistor having the first input gate, a source, and a drain, wherein the source of the first transistor is coupled to a power supply terminal and the drain of the first transistor is coupled to the first terminal of the core;the second transistor of the feedback stage comprises a PMOS transistor having the second input gate, a source, and a drain, wherein the source of the second transistor is coupled to the power supply terminal, the drain of the second transistor is coupled to the second terminal of the core, and the gate of the second transistor is coupled to the gate of the first transistor; andthe output module comprises a second resistive circuit coupled in series with an output PMOS transistor having a gate connected with the first input gate and the second input gate and configured to generate a current copy of the feedback stage and output the current copy as the reference current. 10. The circuit according to claim 1, further comprising a logic circuit, wherein the reference signal comprises a reference voltage and the logic circuit is configured to receive the reference voltage. 11. The circuit according to claim 1, wherein the first stage also includes a third PMOS transistor coupled to the first terminal and a fourth PMOS transistor coupled to the second terminal, wherein conduction paths of the first PMOS transistor, second PMOS transistor, third PMOS transistor, and fourth PMOS transistor are coupled to a reference terminal. 12. A device comprising: a first circuit coupled to terminals of a core and designed to equalize voltages across respective terminals of the core, the core being configured to then be traversed by a first current proportional to absolute temperature, wherein the first circuit comprises a self-biased amplifier, the self-biased amplifier comprising: a first stage arranged according to a folded setup, the first stage comprising first PMOS transistors coupled to the terminals of the core and arranged in a common-gate setup, anda feedback stage having an input coupled to an output of the self-biased amplifier and having an output coupled to an input of the first stage of the self-biased amplifier and to at least one terminal of the core;a second circuit configured to generate a second current inversely proportional to absolute temperature, wherein the second circuit comprises a follower amplifier coupled to a terminal of the core, wherein the follower amplifier is separated from the first stage of the self-biased amplifier; andan output module configured to deliver to an output terminal a reference signal based on a reference current proportional to a sum of the first current and the second current. 13. The device of claim 12, wherein the feedback stage is configured to conduct the reference current, andthe output module and the feedback stage comprise gate connected transistors coupled to a supply voltage terminal and configured to copy the reference current to the output module. 14. The device of claim 12, wherein the second circuit further comprises an additional feedback stage coupled to a first stage of the follower amplifier. 15. The device of claim 14, wherein the first stage of the follower amplifier comprises a differential amplifier having an inverting input terminal coupled to a terminal of the core, a non-inverting input terminal, and an output terminal. 16. The device of claim 15, wherein the additional feedback stage comprises a feedback transistor and a feedback resistor connected in series between a supply voltage terminal and a reference terminal, wherein a gate of the feedback transistor is coupled to the output terminal of the differential amplifier, a first conduction terminal of the feedback transistor is coupled to the supply voltage terminal, and a second conduction terminal of the feedback transistor is coupled to the non-inverting input terminal. 17. The device of claim 14, further comprising a bias loop coupled to the additional feedback stage and the first stage of the self-biased amplifier, wherein the bias loop is configured to be traversed by the second current. 18. The device of claim 17, further comprising a bias current mirror circuit coupled to the first circuit, the second circuit, and the bias loop, wherein the bias current mirror circuit comprises a plurality of gate connected transistors that are configured to be traversed by the second current. 19. The device of claim 12, wherein the core comprises: a core resistor coupled to the feedback stage;a first bipolar junction transistor (BJT) coupled between the core resistor and a reference terminal; anda second BJT coupled between the feedback stage and the reference terminal, wherein a base terminal of the first BJT and a base terminal of the second BJT are both coupled directly to the reference terminal. 20. The device of claim 12, wherein the reference signal comprises the reference current. 21. The device of claim 12, wherein the reference signal comprises a reference voltage. 22. A circuit comprising: a first bipolar junction transistor (BJT) coupled between a first internal terminal and a first reference node;a second BJT coupled between a second internal terminal and the first reference node;a first resistor coupled between the first internal terminal and the first BJT;a first transistor having a conduction path coupled between the first internal terminal and a supply voltage node;a second transistor having a conduction path coupled between the second internal terminal and the supply voltage node;a first P-type MOS transistor having a conduction path coupled between the first internal terminal and gates of the first and second transistors;a second P-type MOS transistor being diode connected and having a conduction path coupled to the second internal terminal; anda follower amplifier having an input coupled to the second internal terminal, wherein the follower amplifier is separate from the first P-type MOS transistor and the second P-type MOS transistor. 23. The circuit of claim 22, wherein the follower amplifier comprises a differential amplifier having an inverting input terminal coupled to the second internal terminal, a non-inverting input terminal, and an output terminal, and a feedback transistor having a first conduction terminal coupled to the supply voltage node, a second conduction terminal coupled to the non-inverting input terminal of the differential amplifier, and a gate coupled to the output terminal of the differential amplifier; and further comprising a second resistor coupled between the second conduction terminal of the feedback transistor and a second reference node. 24. The circuit of claim 23, further comprising: a first bias transistor having a conduction path coupled between the gates of the first and second transistors and the second reference node;a second bias transistor having a conduction path coupled between a conduction terminal of the second P-type MOS transistor and the second reference node;a third bias transistor having a second conduction terminal coupled to the second reference node, and a gate coupled to gates of the first and second bias transistors, wherein the gate of the third bias transistor is further coupled to a first conduction terminal of the third bias transistor;a fourth bias transistor having a conduction path coupled in series with the conduction path of the third bias transistor; anda fifth bias transistor having a conduction path coupled between the supply voltage node and the conduction path of the fourth bias transistor, and a gate coupled to the gate of the feedback transistor. 25. The circuit of claim 23, further comprising: a first output transistor having a conduction path coupled to the supply voltage node and a gate coupled to the gates of the first and second transistors;a second output transistor having a conduction path coupled between a reference output terminal and the conduction path of the first output transistor and a gate coupled to gates of the first P-type MOS transistor the second P-type MOS transistor; anda third resistor coupled between the reference output terminal and the second reference node.
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이 특허에 인용된 특허 (10)
Can Sumer, Bandgap reference voltage circuit with PTAT current source.
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