초록 ▼

Multi-stage power adapter techniques are described in which a power adapter for a device is configured to selectively switch between a relatively low power supply and a relatively high power supply. The low power supply may be employed upon initial connection of the adapter to a host device to ensur

Multi-stage power adapter techniques are described in which a power adapter for a device is configured to selectively switch between a relatively low power supply and a relatively high power supply. The low power supply may be employed upon initial connection of the adapter to a host device to ensure that the adapter is safe when disconnected and does not supply full power before the device is ready to receive the high power supply. The low power supply may supply enough power for the host device to detect the connection of the adapter and establish initial communication with the adapter. A switch to the high power supply by the adapter may then occur in response to a notification from the host device that indicates the host device is ready for the high power supply. The switch to high power supply enables normal operation of the host device.

대표청구항 ▼

1. A power adapter external to a host computing device comprising: a supply circuit configured to supply at least a first power level and a second power level, the first power level supplied to the host computing device to power a microcontroller of the host computing device for performance of power

1. A power adapter external to a host computing device comprising: a supply circuit configured to supply at least a first power level and a second power level, the first power level supplied to the host computing device to power a microcontroller of the host computing device for performance of power management tasks without using a primary processing system integrated into the host computing device, the supply circuit operable to provide different power levels under substantially constant voltage by changing an amount of resistance applied in the supply circuit and thereby vary an amount of current supplied; anda power manager implemented by a microcontroller integrated with the power adapter configured to detect a notification from the host computing device, the notification indicating to the power manager that the host computing device is ready for the second power level to be supplied by the power adapter, and initiate a switch of the supply circuit to the second power level in response to the notification, the second power level supplied to at least the primary processing system of the host computing device. 2. A power adapter as described in claim 1, wherein the notification is a patterned signal generated by a power controller of the host computing device. 3. A power adapter as described in claim 2, wherein the patterned signal comprises a repeating pattern of voltage pulses. 4. A power adapter as described in claim 1, wherein supplying the second power level comprises causing the power adapter to switch from a first power mode to a second power mode by decreasing an amount of resistance applied in the supply circuitry of the power adapter. 5. A power adapter as described in claim 4, wherein the power adapter is configured to implement multiple power modes including the first power mode and the second power mode. 6. A power adapter as described in claim 1, wherein the first power level supplied by the power adapter is sufficient to operate the microcontroller of the host computing device to generate and communicate notifications to cause a switch to a different power level responsive to a determination that the host computing device is ready for the different power level. 7. A power adapter as described in claim 1, the power manager module further configured to recognize an initial connection of the power adapter to a power source and cause the power adapter to supply the first power level until the notification from the host computing device is detected. 8. A power adapter as described in claim 1, wherein: the power adapter incorporates a five pin connector connectable to an adapter interface of the host computing device; andone of the five pins is configured to form a communicative coupling to the host computing device when connected to the adapter interface that is employed to convey the notification from the host computing device to the power adapter. 9. A host computing device comprising: one or more processors, the one or more processors including a power controller configured to operate independently of a primary processing system integrated into the host computing device;one or more computer-readable storage media having stored thereon instructions that, when executed by the one or more processors, cause the processors to:obtain a first power level of two or more power levels from a power adapter external to the host computing device upon connection to the power adapter, the first power level supplied to the host computing device sufficient to operate the power controller of the host computing device to perform power management tasks without supplying power to the primary processing system of the host computing device, the power adapter configured to provide the two or more power levels under substantially constant voltage by changing an amount of resistance applied in a supply circuit and thereby vary an amount of current supplied to the host device;determine whether the host computing device is ready for a second power level from the power adapter based at least in part on data obtained from the power adapter; andresponsive to determining that the host computing device is ready for the second power level from the power adapter: generate a notification for communication to the power adapter for recognition and handling by a power manager module implemented by a microcontroller integrated with the power adapter to cause the power adapter to supply the second power level to at least the primary processing system of the host computing device. 10. A computing device as described in claim 9, wherein the notification comprises an alphanumeric code. 11. A computing device as described in claim 9, wherein the notification comprises a non-random signal pattern. 12. A computing device as described in claim 9, the instructions further causing the processors to communicate the notification to the power adapter via a single pin communication channel established by the connection of the power adapter to the adapter interface. 13. A computing device as described in claim 9, wherein to determine whether the host computing device is ready for the second power level from the power adapter includes ascertaining whether a connector of the power adapter is attached properly to the adapter interface of the host computing device. 14. A computing device as described in claim 9, wherein to determine whether the host computing device is ready for the second power level from the power adapter includes verifying whether power output supplied by the power adapter is compatible with the host computing device. 15. A computing device as described in claim 9, wherein to determine whether the host computing device is ready for the second power level from the power adapter comprises obtaining identifying data from the power adapter to identify a type of adapter associated with the power adapter. 16. The computing device as described in claim 9, the power controller further configured to determine whether the host device is ready for the second power level based on whether the host device is operating on internal battery power, the host device is waking up from sleep mode or hibernation mode, or the host device has run out of battery power. 17. A power adapter for a host computing device comprising: a connector configured to connect the power adapter to the host computing device, the power adapter being external to the host computing device and connectable to an external power source to supply power to the host computing device;a power supply circuit implemented in the power adapter configured to provide two or more power levels under substantially constant voltage by changing an amount of resistance applied in the power supply circuit and thereby vary an amount of current supplied to the host computing device, the two or more power levels including at least a first power level and a second power level, the first power level sufficient to operate a power controller of the host computing device to perform power management tasks and insufficient to power other components of the host computing device; anda power manager implemented by a microcontroller integrated with the power adapter operable to selectively switch between the first power level and the second power level based upon feedback obtained from the host device configured to indicate to the power adapter that the host computing device is ready for the second power level, the feedback communicated by the power controller of the host computing device for recognition and handling by the power manager implemented by the microcontroller of the power adapter, the second power level supplied to at least a primary processing system of the host computing device. 18. A power adapter as described in claim 17, wherein the power manager is configured to cause the amount of resistance applied in the power supply circuit to change by toggling switches to isolate a portion of the circuit or switch between multiple different circuit paths. 19. A power adapter as described in claim 17, wherein the feedback comprises a pulsed voltage signal that is received by the power manager from a power controller of the host computing device, the pulsed voltage signal being communicated by the power controller responsive to a determination that the host computing device is ready for the second power level and configured to cause the power manager module to switch to the second power level.