최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0472108 (2014-08-28) |
등록번호 | US-9305867 (2016-04-05) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 1 인용 특허 : 349 |
An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transisto
An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors and a connection path between the second transistors and the second metal layer, where the connection path includes at least one through-layer via, and where the through-layer via has a diameter less than 150 nm.
1. An Integrated Circuit device, comprising: a first layer comprising first transistors;a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;a second metal layer overlaying said first metal layer; anda second layer comprising second tr
1. An Integrated Circuit device, comprising: a first layer comprising first transistors;a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;a second metal layer overlaying said first metal layer; anda second layer comprising second transistors overlaying said second metal layer, wherein said second metal layer is connected to provide power to at least one of said second transistors; anda connection path between said second transistors and said second metal layer, wherein said connection path comprises at least one through-layer via, andwherein said through-layer via has a diameter less than 150 nm. 2. An Integrated Circuit device according to claim 1, further comprising: logic cells comprising said second transistors, wherein at least one of said logic cells comprises a connection made by said second metal layer. 3. An Integrated Circuit device according to claim 1, wherein at least one of said second transistors comprises a back-bias. 4. An Integrated Circuit device according to claim 1, wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer. 5. An Integrated Circuit device according to claim 1, wherein at least one of said second transistors is one of: (i) a replacement-gate transistor; or(ii) a Finfet transistor. 6. An Integrated Circuit device according to claim 1, further comprising: at least one via through said second layer, wherein said first layer comprises a first alignment mark, andwherein said at least one via is aligned to said first alignment mark. 7. An Integrated Circuit device according to claim 1, further comprising: at least one via through said second layer, wherein said at least one via is adapted to conduct heat. 8. An Integrated Circuit device, comprising: a first layer comprising first transistors;a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;a second metal layer overlaying said first metal layer;a second layer comprising second transistors overlaying said second metal layer; anda third metal layer overlying said second transistors, wherein at least one of said second transistors comprises a significantly different channel material than said first transistors; anda connection path between said second transistors and said second metal layer, wherein said connection path comprises at least one through-layer via, andwherein said through-layer via has a diameter less than 150 nm. 9. An Integrated Circuit device according to claim 8, wherein said second metal layer is connected to provide power to at least one of said second transistors. 10. An Integrated Circuit device according to claim 8, further comprising: at least one via through said second layer, wherein said at least one via is adapted to conduct heat. 11. An Integrated Circuit device according to claim 8, further comprising: at least one via through said second layer, wherein said at least one via is forming a direct contact with at least one of said second transistors. 12. An Integrated Circuit device according to claim 8, wherein at least one of said second transistors is one of: (i) a replacement-gate transistor;(ii) a Finfet transistor; or(iii) a double gate horizontally oriented transistor. 13. An Integrated Circuit device according to claim 8, wherein said first layer comprises a first alignment mark, andwherein said second transistors are aligned to said first alignment mark. 14. An Integrated Circuit device comprising: a first layer comprising first transistors;a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;a second metal layer overlaying said first metal layer;a second layer comprising second transistors overlaying said second metal layer; anda third metal layer overlying said second transistors; anda connection path between said second transistors and said second metal layer, wherein said connection path comprises at least one through-layer via,wherein said through-layer via has a diameter less than 150 nm, andwherein at least one of said second transistors is one of: (i) a replacement-gate transistor;(ii) a Finfet transistor; or(iii) a double gate horizontally oriented transistor. 15. An Integrated Circuit device according to claim 14, further comprising: a back-bias for at least one of said second transistors. 16. An Integrated Circuit device according to claim 14, wherein said second metal layer is connected to provide power to at least one of said second transistors. 17. An Integrated Circuit device according to claim 14, wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer. 18. An Integrated Circuit device according to claim 14, further comprising: vias through said second layer, wherein said vias are adapted to conduct heat. 19. An Integrated Circuit device according to claim 14, further comprising: a plurality of contacts to said second transistors, wherein said first layer comprises a first alignment mark, andwherein said plurality of contacts are lithographically aligned to said first alignment mark. 20. An Integrated Circuit device, comprising: a first layer comprising first transistors;a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;a second metal layer overlaying said first metal layer;a second layer comprising second transistors overlaying said second metal layer; anda third metal layer overlying said second transistors; anda connection path between said second transistors and said second metal layer, wherein said connection path comprises at least one through-layer via,wherein said through-layer via has a diameter less than 250 nm, andwherein at least one of said second transistors is one of: (i) a replacement-gate transistor; or(ii) a Finfet transistor. 21. An Integrated Circuit device according to claim 20, wherein said second metal layer comprises copper or aluminum. 22. An Integrated Circuit device according to claim 20, further comprising: a back-bias for at least one of said second transistors. 23. An Integrated Circuit device according to claim 20, wherein said second metal layer comprises a power grid to provide power to at least one of said second transistors. 24. An Integrated Circuit device according to claim 20, wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer. 25. An Integrated Circuit device according to claim 20, wherein said second layer is less than 200 nm thick.
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