최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0485682 (2014-09-13) |
등록번호 | US-9318974 (2016-04-19) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 3 인용 특허 : 707 |
A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.
1. An apparatus comprising: a multi-level inverter comprising a first phase circuit and a second phase circuit, each of the first and the second phase circuits comprising a flying capacitor circuit;a first set of switches connecting the first phase circuit between voltage input terminals and a secon
1. An apparatus comprising: a multi-level inverter comprising a first phase circuit and a second phase circuit, each of the first and the second phase circuits comprising a flying capacitor circuit;a first set of switches connecting the first phase circuit between voltage input terminals and a second set of switches connecting the second phase circuit between the voltage input terminals; andan interphase balancing circuit comprising a first pair of terminals connected in parallel across the first phase circuit and a second pair of terminals connected in parallel across the second phase circuit. 2. The apparatus of claim 1, further comprising a controller, wherein: the first phase circuit and the second phase circuit each comprise a phase output, an inductor, first and second pairs of switches and first and second capacitors;a first terminal of the inductor is connected to the phase output;a second terminal of the inductor is connected to first terminals of the first pair of switches;the first capacitor is connected across junctions that connect second terminals of the first pair of switches respectively to first terminals of the second pair of switches;the second capacitor is connected across second terminals of the second pair of switches; andthe controller is configured to balance a voltage across the first capacitor. 3. The apparatus of claim 1, further comprising a controller, wherein: the first set of switches comprises at least one high switch connecting a first input terminal of the first phase circuit to a first one of the voltage input terminals and least one low switch connecting a second input terminal of the first phase circuit to a second one of the voltage input terminal;the second set of switches comprises at least one second high switch connecting a first input terminal of the second phase circuit to the first one of the voltage input terminals and least one second low switch connecting a second input terminal of the second phase circuit to the second one of the voltage input terminals; andthe controller is configured to switch the first set of switches and the second set of switches at a lower frequency than switches in first and second phase circuits. 4. The apparatus of claim 1, wherein the interphase balancing circuit comprises: a first switch connecting a high input terminal of the first phase circuit to a low input terminal of the second phase circuit; anda second switch connecting a high input terminal of the second phase circuit to a low input terminal of the first phase circuit. 5. The apparatus of claim 1, further comprising a controller circuit configured to control the first and the second sets of switches at a lower frequency than the first phase circuit and the second phase circuit. 6. The apparatus of claim 1, wherein: the first set of switches comprises a first plurality of high switches connected in series between a first input terminal of the first phase circuit and a first one of the voltage input terminals, and a first plurality of low switches connected in series between a second input terminal of the first phase circuit and a second one of the voltage input terminals; andthe second set of switches comprises a second plurality of high switches connected in series between a first input terminal of the second phase circuit and the first one of the voltage input terminals and a second plurality of low switches connecting a second input terminal of the second phase circuit to the second one of the voltage input terminals. 7. The apparatus of claim 1, wherein the first phase circuit comprises: a first bank and a second bank of series connected switches, wherein the first bank and the second bank are connected in series between the first set of switches; anda plurality of capacitors each connected between one of the series connected switches in the first bank and a corresponding one of the series connected switches in the second bank. 8. The apparatus of claim 7, further comprising: a controller circuit configured to toggle each of a plurality of series connected switches in the first bank at a common duty cycle and at a common frequency, toggle each of the series connected switches in the first bank and its corresponding one of the series connected switches in the second bank in opposite states, and shift a phase of each of the plurality of series connected switches in the first bank by a sequentially increasing amount. 9. The apparatus of claim 8, wherein the controller circuit is configured to adjust switching of at least one of the plurality of series connected switches to a different duty cycle such that voltage across one of the plurality of capacitors is compensated in response to mismatches between those of the series connected switches connected to the one of the plurality of capacitors. 10. The apparatus of claim 8, wherein the controller circuit is configured to adjust the common duty cycle to adjust a conversion ratio of the multi-level inverter. 11. The apparatus of claim 1, wherein the flying capacitor circuit of each of the first and the second phase circuits comprises series connected low voltage MOSFET transistors. 12. The apparatus of claim 11, wherein the flying capacitor circuit of each of the first and the second phase circuits comprises a plurality of switched resistors, each switched resistor of the plurality of switched resistors bypassing one of the low voltage MOSFET transistors. 13. The apparatus of claim 1, further comprising a controller circuit configured to switch the first and the second phase circuits at a cycle frequency of about 50 kHz or about 200 kHz. 14. The apparatus of claim 1, further comprising: one or more additional phase circuits, each comprising a flying capacitor circuit;one or more additional sets of switches respectively connecting the one or more additional phase circuits between the voltage input terminals; andone or more additional pairs of terminals comprised in the interphase balancing circuit and respectively connected across the one or more additional phase circuits. 15. The apparatus of claim 1, further comprising a transformer comprising: a first winding coupled across an output of the first phase circuit and an output of the second phase circuit; anda second winding forming a phase output of the apparatus. 16. The apparatus of claim 1, further comprising first and second transformers, wherein a first winding of the first transformer is conductively coupled to an output of the first phase circuit and a first winding of the second transformer is conductively coupled to an output of the second phase circuit; and a second winding of the first transformer and a second winding of the second transformer form phase outputs of the apparatus. 17. The apparatus of claim 1, wherein the first phase circuit comprises first phase input terminals connected to the first set of switches and to the first pair of terminals of the interphase balancing circuit, and wherein the second phase circuit comprises second phase input terminals connected to the second set of switches and to the second pair of terminals of the interphase balancing circuit. 18. A method comprising: switching a first phase circuit and a second phase circuit of a multilevel inverter at a first frequency;switching a first pair of switches and a second pair of switches of the multilevel inverter at a second frequency, the first pair of switches connecting the first phase circuit between a pair of voltage input terminals and the second pair of switches connecting the second phase circuit between the pair of voltage input terminals; andremoving ripple voltage at the second frequency across the first phase circuit and across the second phase circuit by sharing current between the first phase circuit and second phase circuit. 19. The method of claim 18, further comprising sharing the current between the first phase circuit and the second phase circuit through an interphase balancing circuit that connects a high input terminal of the first phase circuit to a low input terminal of the second phase circuit through a first cross switch, and connects a high input terminal of the second phase circuit to a low input terminal of the first phase circuit through a second cross switch. 20. The method of claim 18, the second frequency being lower than the first frequency. 21. The method of claim 18, operating the multilevel inverter to convert greater than 15 KW of power at greater than 99% efficiency. 22. The method of claim 18, further comprising: toggling each of a first plurality of series connected switches of a first flying capacitor circuit in the first phase circuit and each of a second plurality of series connected switches of a second flying capacitor circuit in the second phase circuit at a common frequency; the first plurality of series connected switches comprising a first plurality of switch pairs; the second plurality of series connected switches comprising a second plurality of switch pairs; and the toggling comprising switching each switch pair in the first plurality of switch pairs in a sequential order phase shifted by a fraction of a switching period, switching each switch pair in the second plurality of switch pairs in the sequential order phase shifted by the fraction of the switching period, maintaining the switches of each switch pair in the first plurality of switch pairs in opposite states, and maintaining the switches of each switch pair in the second plurality of switch pairs in opposite states. 23. The method of claim 22, the fraction of the switching period being equal to the inverse of a number of the switch pairs in the first plurality of switch pairs. 24. The method of claim 22, further comprising adjusting the toggling of the switches in at least one of the switch pairs of the first plurality of switch pairs to different duty cycles such that voltage across one of a plurality of capacitors in the first flying capacitor circuit is compensated in response to mismatches between the at least one of the switch pairs of the first plurality of switch pairs. 25. The method of claim 18, further comprising adjusting duty cycles of the first phase circuit and the second phase circuit such that a conversion ratio of the multilevel inverter is changed.
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