DSSS inverted spreading for smart utility networks
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04B-001/00
H04B-001/707
H04B-001/7085
H04L-005/00
H04L-027/22
출원번호
US-0719405
(2015-05-22)
등록번호
US-9319095
(2016-04-19)
발명자
/ 주소
Schmidl, Timothy Mark
Dabak, Anand G.
출원인 / 주소
TEXAS INSTRUMENTS INCORPORATED
대리인 / 주소
Chan, Tuenlap D.
인용정보
피인용 횟수 :
2인용 특허 :
3
초록▼
A method of operating a transmitter (FIGS. 3A and 5A) is disclosed. The method includes receiving a sequence of data bits (DATA), wherein each data bit has a respective sequence number. A first data bit of the sequence is spread (508) with a first spreading code (504) determined by the sequence numb
A method of operating a transmitter (FIGS. 3A and 5A) is disclosed. The method includes receiving a sequence of data bits (DATA), wherein each data bit has a respective sequence number. A first data bit of the sequence is spread (508) with a first spreading code (504) determined by the sequence number (502) of the first data bit. A second data bit of the sequence is spread (508) with an inverse of the first spreading code (506) determined by the sequence number (502) of the second data bit. The first and second data bits are modulated (510) and transmitted (516) to a remote receiver.
대표청구항▼
1. A transmitter, comprising: a buffer configured to receive a sequence of data bits, each data bit having a respective sequence number;a memory circuit storing a first spreading code and a second spreading code inversing the first spreading code; andan XOR circuit coupled with the buffer, the XOR c
1. A transmitter, comprising: a buffer configured to receive a sequence of data bits, each data bit having a respective sequence number;a memory circuit storing a first spreading code and a second spreading code inversing the first spreading code; andan XOR circuit coupled with the buffer, the XOR circuit configured to:spread a first data bit of the sequence into spread first data bits using the first spreading code determined by the sequence number of the first data bit; andspread a second data bit of the sequence into spread second data bits using the second spreading code determined by the sequence number of the second data bit. 2. The transmitter of claim 1, wherein: the first data bit has an even sequence number; andthe second data bit has an odd sequence number. 3. The transmitter of claim 1, further comprising: a second XOR circuit coupled with the XOR circuit, the second XOR circuit configured to scramble the first and second spread data bits with a scrambling code. 4. The transmitter of claim 1, further comprising: a modulator coupled with the XOR circuit to apply offset quadrature phase shift keyed (O-QPSK) modulation to the spread first and second data bits. 5. The transmitter of claim 1, wherein the first spreading code includes four chips. 6. A transmitter, comprising: a buffer configured to receive a sequence of data bits, each data bit having a respective sequence number;an inverter coupled with the buffer, the inverter configured to invert a first data bit of the sequence in response to the sequence number of the first data bit; andan XOR circuit alternately coupled with the buffer and the inverter to:spread the inverted first data bit into spread first data bits using a spreading code; andspread a second data bit into spread second data bits of the sequence using the spreading code. 7. The transmitter of claim 6, wherein: the first data bit has an odd sequence number; andthe second data bit has an even sequence number. 8. The transmitter of claim 6, further comprising: a second XOR circuit coupled with the XOR circuit, the second XOR circuit configured to scramble the first and second spread data bits with a scrambling code. 9. The transmitter of claim 6, further comprising: a modulator coupled with the XOR circuit to apply offset quadrature phase shift keyed (O-QPSK) modulation to the spread first and second data bits. 10. The transmitter of claim 6, wherein the spreading code includes at least four chips. 11. A receiver, comprising: a memory circuit storing a first despreading code and a second despreading code inversing the first despreading code; andan XOR circuit coupled with the memory circuit, the XOR circuit configured to:receive a first and second groups of spread data bits, each group of spread data bits having a respective sequence number;despread the first group of spread data bits sharing a first sequence number to generate a first data bit using the first despreading code determined by the first sequence number; anddespread the second group of spread data bits to generate a second data bit using the second despreading code. 12. The receiver of claim 11, wherein: the first sequence number is an even number; andthe second sequence number is an odd number. 13. The receiver of claim 11, further comprising: a second XOR circuit coupled with the XOR circuit, the second XOR circuit configured to descramble a first group of scrambled data bits and a second group of scrambled data bits to the first group of spread data bits and the second group of spread data bits respectively with a descrambling code. 14. The receiver of claim 11, further comprising; a demodulator coupled with the XOR circuit to apply offset quadrature phase shift keyed (O-QPSK) demodulation for generating the first and second groups of spread data bits. 15. The receiver of claim 11, in which the first despreading code includes at least four chips. 16. A receiver, comprising: a memory circuit storing a despreading code;an XOR circuit coupled with the memory circuit, the XOR circuit configured to:receive a first and second groups of spread data bits, each group of spread data bits having a respective sequence number;despread the first group of spread data bits to generate a first data bit using a spreading code; anddespread the second group of spread data bits to generate a second data bit using the spreading code; andan inverter coupled with the XOR circuit, the inverter configured to invert the second data bit in response to the sequence number of the second group of spread data bits. 17. The receiver of claim 16, in which; the first group of spread data bits share an even sequence number; andthe second group of spread data bits share an odd sequence number. 18. The receiver of claim 16, further comprising: a second XOR circuit coupled with the XOR circuit, the second XOR circuit configured to descramble a first group of scrambled data bits and a second group of scrambled data bits to the first group of spread data bits and the second group of spread data bits respectively with a descrambling code. 19. The receiver of claim 16, further comprising; a demodulator coupled with the XOR circuit to apply offset quadrature phase shift keyed (O-QPSK) demodulation for generating the first and second groups of spread data bits. 20. The receiver of claim 16, in which the despreading code includes at least four chips.
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