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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0018345 (2013-09-04) |
등록번호 | US-9324811 (2016-04-26) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 38 인용 특허 : 538 |
Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. T
Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.
1. A method of forming a tensile-stressed silicon arsenic layer, the method comprising the steps of: supporting a substrate comprising silicon in a reactor, wherein a surface of the substrate is exposed to a reaction region within the reactor;supplying a silicon source to the reactor;supplying an ar
1. A method of forming a tensile-stressed silicon arsenic layer, the method comprising the steps of: supporting a substrate comprising silicon in a reactor, wherein a surface of the substrate is exposed to a reaction region within the reactor;supplying a silicon source to the reactor;supplying an arsenic source to the reactor; andat a pressure between about 90 Torr and about 300 Torr, forming the tensile-stressed silicon arsenic layer having a concentration of arsenic of greater than 1 E+21 arsenic atoms/cubic centimeter on the surface. 2. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a temperature of the reaction region is between 500° C. and 700° C. 3. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a pressure within the reaction region is between 90 and 300 Torr. 4. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of forming the tensile-stressed silicon arsenic layer, a carrier gas flow rate is between about 10 to about 40 standard liters per minute. 5. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein during the step of supplying an arsenic source to the reactor, arsenic is provided in a non-reactive diluent. 6. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein the step of forming the tensile-stressed silicon arsenic layer comprises epitaxially forming the tensile-stressed silicon arsenic layer on the silicon surface. 7. The method of forming a tensile-stressed silicon arsenic layer of claim 1, wherein the step of forming the tensile-stressed silicon arsenic layer comprises forming a layer comprising greater than or equal to 5 E+21 arsenic atoms/cubic centimeter. 8. The method of forming a tensile-stressed silicon arsenic layer of claim 1, further comprising forming a structure comprising the tensile-stressed silicon arsenic layer. 9. The method of forming a tensile-stressed silicon arsenic layer of claim 1, further comprising forming a device comprising the tensile-stressed silicon arsenic layer. 10. The method of claim 1, wherein the tensile-stressed silicon arsenic layer forms a channel region of a transistor device.
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