Emitter diffusion conditions for black silicon
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/00
H01L-031/18
출원번호
US-0734256
(2015-06-09)
등록번호
US-9324899
(2016-04-26)
발명자
/ 주소
Ahearn, Wendy G.
Levy, David Howard
Topel, Jr., Richard W.
Zubil, Theodore
출원인 / 주소
Natcore Technology, Inc.
대리인 / 주소
Winstead PC
인용정보
피인용 횟수 :
0인용 특허 :
4
초록▼
In some cases, it is desirable to perform doping when manufacturing a solar cell to improve efficiency. Dopant diffusion may include the steps of: (a) an initial temperature ramp, (b) dopant vapor flow, (c) drive-in, and (d) cool down. However, doping may result in excessive doping, such as in regio
In some cases, it is desirable to perform doping when manufacturing a solar cell to improve efficiency. Dopant diffusion may include the steps of: (a) an initial temperature ramp, (b) dopant vapor flow, (c) drive-in, and (d) cool down. However, doping may result in excessive doping, such as in regions where the solar cell has been nanoscale textured to provide black silicon, thereby creating a dead zone with excessive recombination of charge carriers. In the systems and method discussed herein, dopant vapor flow and drive-in steps may be performed at two different temperature set points to minimize or eliminate the formation of dead zones. In some embodiments, the dopant vapor flow may be performed at a lower temperature set point than the drive-in.
대표청구항▼
1. A method for forming a solar cell, the method comprising: depositing a resist layer on a top surface of a substrate, wherein the resist layer serves as a barrier to etching;etching the top surface of the substrate, wherein exposed regions of the substrate are black etched and covered regions with
1. A method for forming a solar cell, the method comprising: depositing a resist layer on a top surface of a substrate, wherein the resist layer serves as a barrier to etching;etching the top surface of the substrate, wherein exposed regions of the substrate are black etched and covered regions with the etching barrier layer remain un-etched;removing the resist layer to expose the covered regions; anddoping the substrate to form an emitter, wherein after doping, the exposed regions have a higher resistivity than un-etched regions. 2. The method of claim 1, wherein the doping comprises the steps of: performing an initial ramp, wherein a substrate temperature is raised to diffusion temperatures during the initial ramp;exposing the substrate to dopant vapor flow during a doping stage;stopping the vapor flow during a drive-in step, exposing the substrate to an inert gas, and raising the temperature of the substrate to drive-in temperatures; andcooling the substrate for a predetermined period of time. 3. The method of claim 2, wherein the initial ramp includes two or more stages of set temperature increases. 4. The method of claim 2, wherein the substrate is exposed to N2 and/or O2 during the initial ramp. 5. The method of claim 2, wherein the substrate is exposed to oxygen after the initial ramp and before the dopant vapor flow. 6. The method of claim 5, wherein the substrate is exposed to the oxygen for 2 minutes or greater before the dopant vapor flow. 7. The method of claim 2, wherein doping temperatures during the doping stage are equal to or between 770 to 830° C. 8. The method of claim 2, wherein the drive-in temperatures are equal to or between 830 to 900° C. 9. The method of claim 2, wherein the drive-in temperatures are 30° C. or greater than doping temperatures during the doping stage. 10. The method of claim 2, wherein the doping stage comprises exposing the substrate to a gas providing phosphorous or a phosphorous containing precursor. 11. The method of claim 2, wherein the substrate is coated with a dopant layer prior to the dopant vapor flow. 12. The method of claim 1 further comprises depositing a dopant barrier layer after the etching step and before removing the resist layer, wherein the dopant barrier layer is self-aligned to the etched regions, and the dopant barrier layer reduces doping in the etched regions. 13. The method of claim 12, wherein the dopant barrier layer is deposited by liquid phase deposition (LPD). 14. The method of claim 12, wherein the dopant barrier layer equal to or less than 50 nm thick. 15. The method of claim 1, wherein the resist layer is a polymer that is not water soluble, and does not degrade, crosslink or harden during the etching step. 16. The method of claim 15, wherein the polymer is comprised of poly(vinylbutyral), poly(vinylacetate), and/or poly(vinylalcohol).
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이 특허에 인용된 특허 (4)
Veerasamy, Vijayen S., Large area deposition and doping of graphene, and products including the same.
Mulligan,William P.; Cudzinovic,Michael J.; Pass,Thomas; Smith,David; Kaminar,Neil; McIntosh,Keith; Swanson,Richard M., Solar cell and method of manufacture.
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