IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0950538
(2013-07-25)
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등록번호 |
US-9336144
(2016-05-10)
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발명자
/ 주소 |
- Buyuktosunoglu, Alper
- Emma, Philip G.
- Hartstein, Allan M.
- Healy, Michael B.
- Kailas, Krishnan K.
|
출원인 / 주소 |
|
대리인 / 주소 |
Scully Scott Murphy and Presser
|
인용정보 |
피인용 횟수 :
0 인용 특허 :
14 |
초록
▼
Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules an
Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations.
대표청구항
▼
1. A processor system, comprising: a plurality of chip layers which are physically conjoined to form a stacked structure,wherein at least one chip layer includes a plurality of processor cores,wherein at least two chip layers include caches that are physically connected through vertical connections
1. A processor system, comprising: a plurality of chip layers which are physically conjoined to form a stacked structure,wherein at least one chip layer includes a plurality of processor cores,wherein at least two chip layers include caches that are physically connected through vertical connections between the at least two chip layers to form one or more cache hierarchies over the at least two chip layers, which am shared by the plurality of processor cores,wherein the one or more cache hierarchies each comprise an L2 cache and an L3 cache, andwherein each cache hierarchy comprises dynamically configurable directories which enables a directory of the L2 cache of a given cache hierarchy to be configured such that a single address in the directory of the L2 cache is mapped to a first cache line in the L2 cache and a second cache line in the L3 cache of the given cache hierarchy. 2. The processor system of claim 1, wherein the one or more cache hierarchies further comprise an L1 cache. 3. The processor system of claim 2, wherein the L1 caches are implemented within the processor cores on a first chip layer, and wherein the L2 caches are implemented on the first chip layer and connected to the L1 caches of processor cores that physically share the L2 caches, and wherein the L3 caches are implemented on a second chip layer and physically connected to the L2 caches. 4. The processor system of claim 3, wherein the L3 caches are victim caches. 5. The processor system of claim 2, wherein the L1 caches are implemented within the processor cores on a first chip layer, and wherein the L2 caches and L3 caches are implemented on a second chip layer. 6. The processor system of claim 5, wherein the L3 caches are victim caches. 7. The processor system of claim 2, wherein the one or more cache hierarchies are inclusive. 8. The processor system of claim 2, wherein the one or more cache hierarchies are non-inclusive. 9. The processor system of claim 1, wherein the plurality of processor cores are grouped into core clusters, wherein each core cluster physically shares one of the L2 and L3 caches. 10. A processor system, comprising: a first chip layer and a second chip layer, which are physically conjoined to form a stacked Structure,the first chip layer including a first cluster of processor cores and a first L2 cache, wherein each processor core in the first cluster of processor cores is physically connected to the first L2 cache; andthe second chip layer including a first L3 cache, which is aligned to the first L2 cache on the first chip layer, wherein the first L3 cache is physically connected to the first L2 cache through vertical connections between the first and second chip layers,wherein the first L2 cache and the first L3 cache form a first cache hierarchy that is physically shared by the first cluster of processor cores, andwherein the first cache hierarchy comprises dynamically configurable directories which enables a directory of the L2 cache of the first cache hierarchy to be configured such that a single address in the directory of the L2 cache is mapped to a first cache line in the L2 cache and a second cache line in the L3 cache of the first cache hierarchy. 11. The processor system of claim 10, wherein the first cache hierarchy is non-inclusive. 12. The processor system of claim 10, wherein the first cache hierarchy is inclusive. 13. The processor system of claim 10, wherein the first L3 cache is a victim cache. 14. The processor system of claim 10, wherein the first chip layer further includes a second cluster of processor cores and a second L2 cache, wherein each processor core in the second cluster of processor cores is physically connected to the second L2 cache, wherein the second chip layer further includes a second L3 cache, which is aligned to the second L2 cache on the first chip layer, wherein the second L3 cache is physically connected to the second L2 cache through vertical connections between the first and second chip layers to form a second cache hierarchy, and wherein the second chip layer further includes an on-chip interconnection network, wherein the first and second L3 caches are connected to the on-chip interconnection network. 15. The processor system of claim 14, wherein the first and second clusters of processor cores logically share the first and second cache hierarchies through the on-chip interconnection network. 16. A processor system, comprising: a first chip layer and a second chip layer, which are physically conjoined to form a stacked structure,the first chip layer including a plurality of processor cores;the second chip layer including a plurality of L2 caches, a plurality of L3 caches, and an on-chip interconnection network,wherein each processor core on the first chip layer is physically connected to a corresponding one of the L2 caches on the second chip layer through vertical connections between the first and second chip layers,wherein each L3 cache is physically connected to, and shared by, at least two L2 caches on the second chip layer, such that each L3 cache is shared by two processor cores,wherein at least one of the L2 caches and one of the L3 caches are configured in a cache hierarchy, andwherein the cache hierarchy comprises dynamically configurable directories which enables a directory of the L2 cache of the cache hierarchy to be configured such that a single address in the directory of the L2 cache is mapped to a first cache line in the L2 cache and a second cache line in the L3 cache of the cache hierarchy. 17. The processor system of claim 16, wherein the L3 caches are connected to the on-chip interconnection network. 18. The processor system of claim 16, wherein the L3 caches are victim caches. 19. The processor system of claim 18, wherein the L2 caches and the L3 caches are connected to the on-chip interconnection network. 20. The processor system of claim 16, wherein the processor cores communicate through the L2 caches and the on-chip interconnection network.
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