High voltage power semiconductor device on SiC
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/00
H01L-029/16
H01L-021/02
H01L-029/04
H01L-029/32
H01L-029/66
H01L-029/868
H01L-029/872
H01L-029/78
출원번호
US-0487774
(2014-09-16)
등록번호
US-9337277
(2016-05-10)
발명자
/ 주소
Loboda, Mark
Chung, Gilyong
출원인 / 주소
DOW CORNING CORPORATION
대리인 / 주소
Nixon Peabody LLP
인용정보
피인용 횟수 :
0인용 특허 :
56
초록▼
4H SIC epiwafers with thickness of 50-100 μm are grown on 4° off-axis substrates. Surface morphological defect density in the range of 2-6 cm−2 is obtained from inspection of the epiwafers. Consistent carrier lifetime in the range of 2-3 μs has been obtained on these epiwafers. Very low BPD density
4H SIC epiwafers with thickness of 50-100 μm are grown on 4° off-axis substrates. Surface morphological defect density in the range of 2-6 cm−2 is obtained from inspection of the epiwafers. Consistent carrier lifetime in the range of 2-3 μs has been obtained on these epiwafers. Very low BPD density has been confirmed in the epiwafers with BPD density down to below 10 cm−2. Epitaxial wafers with thickness of 50-100 μm have been used to fabricate diodes. High voltage testing has demonstrated blocking voltages near the theoretical values for 4H-SiC. Blocking voltage as high as 8 kV has been achieved in devices fabricated on 50 μm thick epitaxial films, and blocking voltage as high as 10 kV has been obtained in devices fabricated on 80 μm thick films. Failure analysis confirmed triangle defects, which form from surface damage or particles present during epitaxy, are killer defects and cause the device to fail in reverse bias operation. In addition, the leakage current at the high blocking voltages of the JBS diodes showed no correlation with the screw dislocation density. It is also observed that the main source of basal plane dislocations in the epilayer originates in the crystal growth process.
대표청구항▼
1. A high voltage semiconductor device comprising: a single crystal 4H-SiC substrate having an area of 0.02 to 1.5 cm2 having: a basal plane dislocation density of less than 2000/cm2; anda plurality of epitaxial layers over the substrate, wherein at least one of the plurality of epitaxial layers has
1. A high voltage semiconductor device comprising: a single crystal 4H-SiC substrate having an area of 0.02 to 1.5 cm2 having: a basal plane dislocation density of less than 2000/cm2; anda plurality of epitaxial layers over the substrate, wherein at least one of the plurality of epitaxial layers has: a net carrier concentration in the range from 1×1014/cm3 to 2×1016/cm3,a micropipe density of less than 1/cm2,a screw dislocation density of less than 2000/cm2, anda basal plane dislocation density of less than 10/cm2. 2. The high voltage semiconductor device of claim 1, wherein the single crystal 4H-SiC substrate having the area of 0.02 to 1.5 cm2 has: a micropipe density of less than 1/cm2, anda screw dislocation density of less than 2000/cm2. 3. The high voltage semiconductor device of claim 1, further comprising at least one p-n junction formed by two adjacent epitaxial layers. 4. The high voltage semiconductor device of claim 1, further comprising at least one epitaxial layer with carrier lifetime of more than 1 microsecond. 5. The high voltage semiconductor device of claim 1, wherein reverse bias blocking voltage, represented as the maximum voltage measured at a leakage current of less than or equal to 10 mA/cm2, is in the range of more than 85% of the theoretical value determined by modeling the device using SiC materials constants. 6. The high voltage device of claim 1, wherein the single crystal 4H-SiC substrate is a single crystal, 4° off-axis 4H-SiC substrate cut at an angle tilted away from the c-axis. 7. The high voltage semiconductor device of claim 1, wherein the single crystal 4H-SiC substrate is a single crystal, 4° off-axis 4H-SiC substrate cut at an angle tilted toward the direction. 8. A method for manufacturing a semiconductor device, comprising: slicing a single crystal 4H-SiC from a single crystal grown by physical vapor transport, the substrate having a basal plane dislocation density of less than 2000/cm2; and depositing a plurality of epitaxial layers over the substrate, wherein at least one of the plurality of epitaxial layers has: a net carrier concentration in the range from 1×1014/cm3 to 2×1016/cm3,a micropipe density of less than 1/cm2,a screw dislocation density of less than 2000/cm2, anda basal plane dislocation density of less than 10/cm2,and fabricating a plurality of devices on top of the epitaxial layers where the devices have an area of 0.02 to 1.5 cm2. 9. The method of claim 8, wherein the single crystal 4H-SiC substrate within the device area of 0.02 to 1.5 cm2 has: a micropipe density of less than 1/cm2, anda screw dislocation density of less than 2000/cm2. 10. The method of claim 8, wherein the step of depositing the plurality of epitaxial layers further comprises forming at least one p-n junction. 11. The method of claim 8, wherein the single crystal 4H-SiC substrate is a single crystal, 4° off-axis 4H-SiC substrate cut at an angle tilted away from the c-axis. 12. The high voltage semiconductor device of claim 8, wherein the single crystal 4H-SiC substrate is a single crystal, 4° off-axis 4H-SiC substrate cut at an angle tilted toward the direction. 13. A method for preparing an SiC substrate, comprising: using a physical vapor transport apparatus to grow a single crystal boule;slicing the boule to obtain a single crystal wafer cut at 4° off-axis and at an angle tilted toward the direction; and,depositing at least one epitaxial layer over the single crystal wafer. 14. The method of claim 13, wherein one of the epitaxial layers has carrier lifetime of more than 1 microsecond. 15. The method of claim 14, wherein the wafer has: a micropipe density of less than 1/cm2, anda screw dislocation density of less than 2000/cm2. 16. The method of claim 15, further comprising depositing a plurality of epitaxial layers over the wafer so as to enable the fabrication of one of: JBS Diode, MOSFET or PiN Diode. 17. The method of claim 15, wherein the at least one epitaxial layer is one of a plurality of epitaxial layers formed over the wafer, and has: a net carrier concentration in the range from 1×1014/cm3 to 2×1016/cm3,a micropipe density of less than 1/cm2,a screw dislocation density of less than 2000/cm2, anda basal plane dislocation density of less than 10/cm2. 18. A high voltage semiconductor device having an area of 0.02 to 1.5 cm2 comprising: a single crystal 4H-SiC substrate ha cut at 4° off-axis and at an angle tilted toward the direction; anda plurality of epitaxial layers over the substrate configured for forming one of JBS Diode, MOSFET or PiN Diode. 19. The device of claim 18, wherein at least one of the plurality of epitaxial layers has: a net carrier concentration in the range from 1×1014/cm3 to 2×1016/cm3,a micropipe density of less than 1/cm2,a screw dislocation density of less than 2000/cm2, and a basal plane dislocation density of less than 10/cm2. 20. The device of claim 18, wherein the device has: an area of 0.02 to 1.5 cm2,a micropipe density of less than 1/cm2, anda screw dislocation density of less than 2000/cm2.
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