[특허]Circuits for and methods of providing voltage level shifting in an integrated circuit device

Circuits for and methods of providing voltage level shifting in an integrated circuit device 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03L-005/00 H03K-019/0185
출원번호	US-0507260 (2014-10-06)
등록번호	US-9337841 (2016-05-10)
발명자 / 주소	Sood, Santosh Kumar
출원인 / 주소	XILINX, INC.
대리인 / 주소	King, John J.
인용정보	피인용 횟수 : 0 인용 특허 : 35

초록 ▼

A circuit for providing voltage level shifting in an integrated circuit includes an inverter having an input coupled to receive an input signal having a first voltage level; an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level. A gate of the second transistor is coupled to an output of the inverter. A pull-up transistor is coupled between a reference voltage having the second voltage level and a gate of the first transistor. A switch is coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the gate of the first transistor. A method of providing voltage level shifting in an integrated circuit is also disclosed.

대표청구항 ▼

1. A circuit for providing voltage level shifting, the circuit comprising: an inverter having an input coupled to receive an input signal having a first voltage level;an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level;wherein a gate of the second transistor is coupled to an output of the inverter;a pull-up transistor coupled between a reference voltage having the second voltage level and a gate of the first transistor; anda switch coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the gate of the first transistor, wherein: the first transistor comprises a first p-channel transistor;the second transistor comprises a first n-channel transistor; andthe switch comprises a second p-channel transistor coupled in parallel with a second n-channel transistor. 2. The circuit of claim 1, wherein a drain of the second n-channel transistor and a source of the second p-channel transistor are coupled to the gate of the first p-channel transistor. 3. The circuit of claim 2, wherein a source of the second n-channel transistor and a drain of the second p-channel transistor are coupled to the gate of the first n-channel transistor. 4. The circuit of claim 1, wherein a gate of the second n-channel transistor is coupled to the input of the inverter. 5. The circuit of claim 4, wherein a gate of the second p-channel transistor is coupled to the gate of the first p-channel transistor. 6. The circuit of claim 1, wherein the output node is coupled to a gate of the pull-up transistor. 7. An integrated circuit comprising: a first circuit block configured to receive a first reference signal having a first voltage level;a second circuit block configured to receive a second reference signal having a second voltage level; anda voltage level shifting circuit coupled to at least one of the first circuit block or the second circuit block, the voltage level shifting circuit comprising: an inverter having an input coupled to receive an input signal having the first voltage level;an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having the second voltage level;wherein a gate of the second transistor is coupled to an output of the inverter;a pull-up transistor coupled between a reference voltage having the second voltage level and a gate of the first transistor; anda switch coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the gate of the first transistor, wherein: the first transistor comprises a first p-channel transistor;the second transistor comprises a first n-channel transistor; andthe switch comprises a second p-channel transistor coupled in parallel with a second n-channel transistor. 8. The circuit of claim 7, wherein: a drain of the second n-channel transistor and a source of the second p-channel transistor are coupled to the gate of the first p-channel transistor; anda source of the second n-channel transistor and a drain of the second p-channel transistor are coupled to the gate of the first n-channel transistor. 9. The circuit of claim 7, wherein: a gate of the second n-channel transistor is coupled to the input of the inverter; anda gate of the second p-channel transistor is coupled to the gate of the first p-channel transistor. 10. The circuit of claim 7, wherein the output node is coupled to a gate of the pull-up transistor. 11. The circuit of claim 7, wherein the first circuit block comprises a configurable logic element and the voltage level shifting circuit. 12. The circuit of claim 7, further comprising: a plurality of circuit blocks including the first circuit block and the second circuit block, wherein each circuit block of the plurality of circuit blocks includes a configurable logic element and a level shifting circuit. 13. The circuit of claim 7, wherein the second circuit block comprises a configurable logic element and the voltage level shifting circuit. 14. A method of providing voltage level shifting in an integrated circuit, the method comprising: coupling an input signal having a first voltage level to an input of an inverter;coupling a first transistor of an output stage in series with a second transistor of the output stage;coupling a gate of the second transistor to an output of the inverter;coupling a pull-up transistor between a reference voltage having a second voltage level and a gate of the first transistor;controlling the voltage at the gate of the first transistor with a switch coupled between the gate of the first transistor and the gate of the second transistor, wherein the switch comprises a p-channel transistor coupled in parallel with an n-channel transistor; andgenerating an output signal having the second voltage level at an output node between the first transistor and the second transistor. 15. The method of claim 14, further comprising: coupling a drain of the n-channel transistor and a source of the p-channel transistor to the gate of the first transistor; andcoupling a source of the n-channel transistor and a drain of the p-channel transistor are to the gate of the second transistor. 16. The method of claim 14, further comprising: coupling a gate of the n channel transistor to the input of the inverter; andcoupling a gate of the p channel transistor to the gate of the first transistor. 17. The method of claim 14, further comprising coupling the output signal at the output node to a gate of the pull-up transistor. 18. The method of claim 14, further comprising: implementing a plurality of circuit blocks in the integrated circuit;wherein each circuit block of the plurality of circuit blocks includes a configurable logic element and a level shifting circuit.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Circuits for and methods of providing voltage level shifting in an integrated circuit device 원문보기

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Circuits for and methods of providing voltage level shifting in an integrated circuit device 원문보기

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이 특허에 인용된 특허 (35)

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