Horizontally oriented and vertically stacked memory cells
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/02
H01L-045/00
H01L-027/24
출원번호
US-0688502
(2015-04-16)
등록번호
US-9349949
(2016-05-24)
발명자
/ 주소
Quick, Timothy A.
Marsh, Eugene P.
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
Brooks, Cameron & Huebsch, PLLC
인용정보
피인용 횟수 :
0인용 특허 :
106
초록▼
Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell materi
Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.
대표청구항▼
1. A memory device, comprising: a memory cell, wherein the memory cell includes: a first insulator material;a memory cell material formed on the first insulator material, wherein the memory cell material has a recess formed therein;a second insulator material formed on the memory cell material;a fir
1. A memory device, comprising: a memory cell, wherein the memory cell includes: a first insulator material;a memory cell material formed on the first insulator material, wherein the memory cell material has a recess formed therein;a second insulator material formed on the memory cell material;a first electrode adjacent a first side of the memory cell material; anda second electrode conformally deposited in the recess and adjacent a second side of the memory cell material. 2. The memory device of claim 1, wherein the memory device includes an additional memory cell vertically stacked on the memory cell, wherein the additional memory cell includes: a memory cell material having a recess formed therein;a first electrode adjacent a first side of the memory cell material; anda second electrode in the recess and adjacent a second side of the memory cell material. 3. The memory device of claim 2, wherein the second insulator material is between the memory cell material of the memory cell and the memory cell material of the additional memory cell. 4. The memory device of claim 1, wherein: the first electrode is in direct contact with a single first side of the memory cell material; andthe second electrode is in direct contact with a single second side of the memory cell material. 5. The memory device of claim 1, wherein the first side of the memory cell material is opposite the second side of the memory cell material. 6. A memory device, comprising: at least two vertically stacked memory cells, wherein each of the memory cells include: a first insulator material;a memory cell material formed on the first insulator material, wherein the memory cell material has a recess formed therein;a first electrode adjacent a first side of the memory cell material; anda second electrode conformally deposited in the recess and adjacent a second side of the memory cell material. 7. The memory device of claim 6, wherein: the at least two vertically stacked memory cells form a first vertical stack of memory cells; andthe memory device includes a second vertical stack of memory cells, wherein each of the memory cells of the second vertical stack include: a memory cell material having a recess formed therein;a first electrode adjacent a first side of the memory cell material; anda second electrode in the recess and adjacent a second side of the memory cell material. 8. The memory device of claim 7, wherein the memory device includes a third insulator material between the first vertical stack of memory cells and the second vertical stack of memory cells. 9. The memory device of claim 6, wherein the memory cell material is a resistive memory cell material. 10. The memory device of claim 6, wherein the first electrode is an access device contact. 11. The memory device of claim 6, wherein the second electrode is a metal material. 12. The memory device of claim 11, wherein the metal material is a portion of a data line of the memory device. 13. The memory device of claim 6, wherein each of the memory cells are horizontally oriented memory cells. 14. A method of processing a memory device, comprising: forming a recess in a memory cell material, wherein forming the recess in the memory cell material includes selectively removing a portion of the memory cell material;forming a first electrode adjacent a first side of the memory cell material; andforming a second electrode in the recess and adjacent a second side of the memory cell material. 15. The method of claim 14 wherein forming the second electrode in the recess includes conformally depositing the second electrode in the recess. 16. The method of claim 14, wherein the method includes: forming the memory cell material on a first insulator material; andforming a second insulator material on the memory cell material. 17. The method of claim 16, wherein the method includes: forming the memory cell material on the first insulator material in situ; andforming the second insulator material on the memory cell material in situ. 18. The method of claim 16, wherein the method includes: forming the memory cell material on the first insulator material using physical vapor deposition; andforming the second insulator material on the memory cell material using physical vapor deposition. 19. The method of claim 16, wherein the method includes: forming an additional memory cell material on the second insulator material; andforming a recess in the additional memory cell material; andforming an electrode in the recess and adjacent a side of the additional memory cell material. 20. A method of processing a memory device, comprising: forming a recess in a memory cell material;forming a first electrode adjacent a first side of the memory cell material; andforming a second electrode in the recess and adjacent a second side of the memory cell material, wherein forming the second electrode in the recess includes conformally depositing the second electrode in the recess.
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