초록 ▼

A method for asynchronous time multiplexing of information with synchronous interfacing includes, responsive to a first edge of a clock signal, asynchronously loading first data, including first multiple sets of data for multiple operations, into a first asynchronous shift register. The first data i

A method for asynchronous time multiplexing of information with synchronous interfacing includes, responsive to a first edge of a clock signal, asynchronously loading first data, including first multiple sets of data for multiple operations, into a first asynchronous shift register. The first data is asynchronously unloaded from the first asynchronous shift register to a function block for processing to provide second data, including second multiple sets of data as results of the multiple operations. The second data is asynchronously loaded into a second asynchronous shift register. Responsive to a second edge of the clock signal, the second data is asynchronously unloaded from the second asynchronous shift register as the results of the multiple operations. The first edge and the second edge of the clock signal are associated with a same period of the clock signal.

대표청구항 ▼

1. A method for asynchronous time multiplexing of information with synchronous interfacing, comprising: receiving a clock signal;responsive to a first edge of the clock signal, asynchronously loading first data into a first asynchronous shift register;wherein the first data includes first multiple s

1. A method for asynchronous time multiplexing of information with synchronous interfacing, comprising: receiving a clock signal;responsive to a first edge of the clock signal, asynchronously loading first data into a first asynchronous shift register;wherein the first data includes first multiple sets of data for multiple operations;asynchronously unloading the first data from the first asynchronous shift register to a function block;processing the first data with the function block to provide second data;wherein the second data includes second multiple sets of data as results for the multiple operations;asynchronously loading the second data into a second asynchronous shift register; andresponsive to a second edge of the clock signal, asynchronously unloading the second data from the second asynchronous shift register as the results of the multiple operations;wherein the first edge and the second edge of the clock signal are associated with a same period of the clock signal. 2. The method according to claim 1, further comprising: responsive to the first edge of the clock signal, asserting a first request signal by a synchronous-to-asynchronous converter to the first asynchronous shift register;wherein the asynchronously loading of the first data into the first asynchronous shift register is responsive to assertion of the first request signal. 3. The method according to claim 2, further comprising: sending a first acknowledgement signal from the first asynchronous shift register to the synchronous-to-asynchronous converter; andde-asserting the first request signal by the synchronous-to-asynchronous converter responsive to the first acknowledgement signal;wherein the asynchronously unloading of the first data is from the first asynchronous shift register to a function block responsive to de-assertion of the first request signal. 4. The method according to claim 3, further comprising: asserting an unload signal by an asynchronous-to-synchronous converter responsive to the second edge of the clock signal and a condition of the second asynchronous shift register; andasserting a second request signal by the second asynchronous shift register to the asynchronous-to-synchronous converter responsive to assertion of the unload signal. 5. The method according to claim 4, further comprising: sending a second acknowledgement signal by the asynchronous-to-synchronous converter to the second asynchronous shift register in response to the second request signal;wherein the asynchronously unloading by the second asynchronous shift register is in response to the second acknowledgement signal; andde-asserting the second request signal by the second asynchronous shift register responsive to the second acknowledgement signal. 6. The method according to claim 5, further comprising: clearing the unload signal by the second asynchronous shift register responsive to the second acknowledgement signal. 7. The method according to claim 1, further comprising for the first data being an initial set of data, adding at least one clock cycle of latency from the asynchronously loading of the first data to the asynchronously unloading of the second data. 8. The method according to claim 1, further comprising: entering a feedback mode; andfeeding back the second data as the first data. 9. A method for asynchronous time multiplexing of information with synchronous interfacing; comprising: receiving a clock signal;responsive to a first edge of the clock signal, initiating a first request;loading multiple sets of inputs via an input data interface;acknowledging the loading;sequentially processing each of the multiple sets of inputs to provide respective sets of outputs;temporarily storing the sets of outputs;initiating a second request responsive to storage of the sets of outputs; andresponsive to a second edge of the clock signal and the second request, unloading the sets of outputs via an output data interface;wherein the sequentially processing of the multiple sets of inputs is asynchronously time multiplexed; andwherein the input data interface and the output data interface appear synchronous with respect to the clock signal. 10. The method according to claim 9, wherein the input data interface and the output data interface are for parallel data input and parallel data output, respectively. 11. The method according to claim 10, further comprising: asynchronously shifting in the multiple sets of inputs with the loading as first parallel data;asynchronously shifting out the multiple sets of inputs sequentially as M-bit wide first serial data for the sequentially processing thereof for M a positive integer greater than 1;asynchronously shifting in the sets of outputs as Q-bit wide second serial data for the temporarily storing for Q a positive integer greater than 1; andasynchronously shifting out the sets of outputs for the unloading as second parallel data. 12. The method according to claim 10, wherein the unloading of the sets of outputs is delayed by at least one clock cycle of the clock signal. 13. The method according to claim 10, further comprising: entering a feedback mode; andfeeding back the sets of outputs unloaded as the multiple sets of inputs for the loading anew. 14. A circuit for asynchronous time multiplexing with synchronous interfacing, comprising: a synchronous-to-asynchronous converter to receive a clock signal to cause first parallel data to be loaded;a first asynchronous shift register to shift in the first parallel data and to shift out first serial data therefrom;a function block to process the first serial data to provide second serial data;a second asynchronous shift register to shift in the second serial data and to shift out second parallel data therefrom; andan asynchronous-to-synchronous converter to receive the clock signal to cause the second parallel data to be unloaded;wherein asynchronous pipelining of the first serial data and the second serial data from the first asynchronous shift register to the second asynchronous shift register provides for asynchronously time multiplexing multiple operations associated with multiple sets of data of the first parallel data. 15. The circuit according to claim 14, wherein the first parallel data is loaded and the second parallel data is unloaded in synchronous operation with respect to the clock signal. 16. The circuit according to claim 15, further comprising: a buffer coupled between the first asynchronous shift register and the second asynchronous shift register and further coupled between a first operator and a second operator of the function block;a first delay coupled between the first asynchronous shift register and the buffer; anda second delay coupled between the buffer and the second asynchronous shift register;wherein a multistage asynchronous pipeline is provided. 17. The circuit according to claim 16, wherein: the buffer is to receive interim data from the first operator for temporary storage and to provide the interim data to the second operator after being temporarily stored;the first delay has a first delay associated with the first operator; andthe second delay has a second delay associated with the second operator. 18. The circuit according to claim 17, wherein the buffer, the first delay, and the second delay are coupled such that: first request signaling goes from the first asynchronous shift register to the first delay and from the first delay to the buffer;second request signaling goes from the buffer to the second delay and from the second delay to the second asynchronous shift register;first acknowledge signaling goes from the second asynchronous shift register to the second delay and from the second delay to the buffer; andsecond acknowledge signaling goes from the buffer to the first delay and from the first delay to the first asynchronous shift register. 19. The circuit according to claim 14, wherein: the second asynchronous shift register has an output data interface coupled to an input data interface of the first asynchronous shift register for operation in a feedback mode; andthe asynchronous-to-synchronous converter is configured to provide a request signal to the first asynchronous shift register and the second asynchronous shift register for selecting between the feedback mode and a feed forward mode. 20. The circuit according to claim 14, wherein the asynchronous-to-synchronous converter is configured to add at least one clock cycle of the clock signal for latency on an initial set of data be processed.