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Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channe

Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.

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1. A method for fabricating an integrated circuit transistor structure comprising steps of: providing an intermediate structure comprising: a body of material, the body having an adjustment layer comprising adjustment volume material, and an upper layer of semiconductor material, the upper layer ove

1. A method for fabricating an integrated circuit transistor structure comprising steps of: providing an intermediate structure comprising: a body of material, the body having an adjustment layer comprising adjustment volume material, and an upper layer of semiconductor material, the upper layer overlying the adjustment layer,a gate conductor outside the body, the gate conductor having portions facing the body on at least three sides of the body and defining a channel volume of the body, the body having first and second longitudinally opposite end surfaces, the gate conductor extending beyond the body in both longitudinal directions, anda dielectric material between the gate conductor and the body;forming first and second additional semiconductor material on respectively the first and second end surfaces of the body; andforming source and drain volumes longitudinally adjacent to respectively the first and second additional semiconductor material,wherein the adjustment volume material has, at each longitudinal position, an electrical conductivity which differs from that of the upper layer of semiconductor material at the same longitudinal position, at least while the transistor is in an off-state,wherein the first additional material is less conductive than the source material, at least when the transistor is in the off state,and wherein the second additional material is less conductive than the drain material, at least when the transistor is in the off state. 2. The method of claim 1, wherein the adjustment volume material comprises a dielectric. 3. The method of claim 1, wherein the adjustment volume material comprises an electrical conductor. 4. The method of claim 1, wherein the adjustment volume material comprises a material having a bandgap which is wider than that of the semiconductor material in the upper layer. 5. The method of claim 1, wherein the adjustment volume material comprises a plurality of sub-layers of material. 6. The method of claim 1, wherein the body of material further has a lower layer of semiconductor material underlying the adjustment layer. 7. The method of claim 6, wherein the upper and lower layers of semiconductor material are the same. 8. The method of claim 1, wherein the adjustment volume material in the body of material is spaced laterally from the dielectric material by a further material that includes a semiconductor. 9. The method of claim 1, further comprising a step of forming further semiconductor material laterally between the body and the dielectric material. 10. The method of claim 1, wherein the second additional material is a semiconductor material with a doping type that is opposite that of the source and drain materials, respectively. 11. A wafer comprising a first plurality of parallel ridges formed on a substrate, wherein each of the ridges comprises: an adjustment layer including adjustment volume material; andan upper layer of semiconductor material overlying the adjustment layer,wherein the adjustment volume material comprises semiconductor material,and wherein the ridges are epitaxially grown in such a way that the adjustment volume material is doped more heavily than all layers of semiconductor material above the adjustment layer. 12. The wafer of claim 11, wherein each of the ridges has two laterally opposing surfaces, further comprising, on each of the laterally opposing surfaces, a semiconductor material which is less heavily doped than the adjustment volume material. 13. The wafer of claim 11, wherein the adjustment volume material comprises a plurality of sub-layers of material. 14. The wafer of claim 11, wherein each of the ridges further has a lower layer of semiconductor material underlying the adjustment layer. 15. The wafer of claim 14, wherein the upper and lower layers of semiconductor material are the same. 16. The wafer of claim 14, wherein the ridges are epitaxially grown in such a way that the adjustment volume material is doped more heavily also than the lower layer of semiconductor material. 17. The wafer of claim 11, wherein each of the ridges further has gate stack material formed thereon. 18. The wafer of claim 11, wherein all the ridges in the first plurality of parallel ridges extend substantially all the way across the substrate. 19. The wafer of claim 11, further comprising a second plurality of ridges formed on the substrate. 20. The wafer of claim 11, wherein the substrate is scribed into dice, and wherein all the ridges in the first plurality of parallel ridges extend only within a first one of the dice and extend substantially all the way across the first die. 21. The wafer of claim 11, wherein the substrate is scribed into dice, further comprising a second plurality of ridges formed on the substrate,wherein all the ridges in the first plurality of parallel ridges extend only within a first one of the dice and all the ridges in the second plurality of parallel ridges extend only within a second one of the dice. 22. A method for fabricating a wafer comprising: forming a first plurality of parallel ridges on a substrate, wherein each of the ridges includes an adjustment layer including adjustment volume material and an upper layer of semiconductor material overlying the adjustment layer,wherein the adjustment volume material comprises semiconductor material,and wherein the ridges are epitaxially grown in such a way that the adjustment volume material is doped more heavily than all layers of semiconductor material above the adjustment layer. 23. The method of claim 22, wherein each of the ridges has two laterally opposing surfaces, further comprising forming, on each of the laterally opposing surfaces, a semiconductor material which is less heavily doped than the adjustment volume material. 24. The method of claim 22, wherein the adjustment volume material includes a plurality of sub-layers of material. 25. The method of claim 22, wherein each of the ridges further has a lower layer of semiconductor material underlying the adjustment layer. 26. The method of claim 25, wherein the upper and lower layers of semiconductor material are the same. 27. The method of claim 25, wherein the ridges are epitaxially grown in such a way that the adjustment volume material is doped more heavily also than the lower layer of semiconductor material. 28. The method of claim 22, further comprising forming gate stack material on each of the ridges. 29. The method of claim 22, wherein all the ridges in the first plurality of parallel ridges extend substantially all the way across the substrate. 30. The method of claim 22, further comprising forming a second plurality of ridges formed on the substrate. 31. The method of claim 22, further comprising scribing the substrate into dice, and wherein all the ridges in the first plurality of parallel ridges extend only within a first one of the dice and extend substantially all the way across the first die. 32. The method of claim 22, further comprising scribing the substrate into dice, and further comprising forming a second plurality of ridges on the substrate,wherein all the ridges in the first plurality of parallel ridges extend only within a first one of the dice and all the ridges in the second plurality of parallel ridges extend only within a second one of the dice. 33. A wafer comprising a first plurality of parallel ridges formed on a substrate, wherein each of the ridges comprises: an adjustment layer including adjustment volume material; andan upper layer of semiconductor material overlying the adjustment layer, the upper layer of semiconductor material having a bandgap which is no wider than that of GaP,wherein the adjustment volume material comprises semiconductor material,and wherein the ridges are epitaxially grown in such a way that the adjustment volume material is doped more heavily than the upper layer of semiconductor material. 34. The wafer of claim 33, wherein each of the ridges has two laterally opposing surfaces, further comprising, on each of the laterally opposing surfaces, a semiconductor material which is less heavily doped than the adjustment volume material. 35. The wafer of claim 33, wherein the adjustment volume material comprises a plurality of sub-layers of material. 36. The wafer of claim 33, wherein each of the ridges further has a lower layer of semiconductor material underlying the adjustment layer. 37. The wafer of claim 36, wherein the upper and lower layers of semiconductor material are the same. 38. The wafer of claim 36, wherein the ridges are epitaxially grown in such a way that the adjustment volume material is doped more heavily also than the lower layer of semiconductor material. 39. The wafer of claim 33, wherein each of the ridges further has gate stack material formed thereon. 40. The wafer of claim 33, wherein all the ridges in the first plurality of parallel ridges extend substantially all the way across the substrate. 41. The wafer of claim 33, further comprising a second plurality of ridges formed on the substrate. 42. The wafer of claim 33, wherein the substrate is scribed into dice, and wherein all the ridges in the first plurality of parallel ridges extend only within a first one of the dice and extend substantially all the way across the first die. 43. The wafer of claim 33, wherein the substrate is scribed into dice, further comprising a second plurality of ridges formed on the substrate,wherein all the ridges in the first plurality of parallel ridges extend only within a first one of the dice and all the ridges in the second plurality of parallel ridges extend only within a second one of the dice. 44. A method for fabricating a wafer comprising: forming a first plurality of parallel ridges on a substrate, wherein each of the ridges includes an adjustment layer including adjustment volume material and an upper layer of semiconductor material overlying the adjustment layer,wherein the upper layer of semiconductor material has a bandgap which is no wider than that of GaP,wherein the adjustment volume material comprises semiconductor material,and wherein the ridges are epitaxially grown in such a way that the adjustment volume material is doped more heavily than the upper layer of semiconductor material. 45. The method of claim 44, wherein each of the ridges has two laterally opposing surfaces, further comprising forming, on each of the laterally opposing surfaces, a semiconductor material which is less heavily doped than the adjustment volume material. 46. The method of claim 44, wherein the adjustment volume material includes a plurality of sub-layers of material. 47. The method of claim 44, wherein each of the ridges further has a lower layer of semiconductor material underlying the adjustment layer. 48. The method of claim 47, wherein the upper and lower layers of semiconductor material are the same. 49. The method of claim 47, wherein the ridges are epitaxially grown in such a way that the adjustment volume material is doped more heavily also than the lower layer of semiconductor material. 50. The method of claim 44, further comprising forming gate stack material on each of the ridges. 51. The method of claim 44, wherein all the ridges in the first plurality of parallel ridges extend substantially all the way across the substrate. 52. The method of claim 44, further comprising forming a second plurality of ridges formed on the substrate. 53. The method of claim 34, further comprising scribing the substrate into dice, and wherein all the ridges in the first plurality of parallel ridges extend only within a first one of the dice and extend substantially all the way across the first die. 54. A method for designing a first integrated circuit transistor, wherein the first transistor is to include: a body of semiconductor material, the body having first and second longitudinally spaced doped source/drain volumes and further having at least a first surface, the body further having a channel volume located longitudinally between the first and second source/drain volumes,a gate conductor disposed outside the body, the gate conductor having a first portion facing the first surface and being located longitudinally at least partly along at least part of the channel volume, anda dielectric material between the gate conductor and the first surface of the body,the body containing an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance, spaced longitudinally from the first source/drain volume by a second distance, and spaced longitudinally from the second source/drain volume,the adjustment volume comprising an adjustment volume material having an electrical conductivity which differs from that of the adjacent body material at each longitudinal position, at least while the first transistor is in an off-state;the method comprising the steps of: choosing for the first transistor, in dependence upon at least one of the factors in the group consisting of desired switching speed, desired leakage current, desired Ion/Ioff ratio and desired mechanical stress, values for at least one of the parameters in the group consisting of: the first distance,the second distance,adjustment material conductivity, andthe adjustment volume material; andimplementing the chosen values in the design of the first transistor. 55. The method of claim 54, wherein choosing for the first transistor, is performed in dependence upon at least one of the factors in the group consisting of desired switching speed, desired leakage current, and desired Ion/Ioff ratio for the first transistor. 56. The method of claim 54, wherein choosing for the first transistor, is performed in dependence upon desired mechanical stress for the first transistor. 57. The method of claim 54, wherein choosing for the first transistor, includes choosing a value for the first distance. 58. The method of claim 54, wherein choosing for the first transistor, includes choosing a value for the second distance. 59. The method of claim 54, wherein choosing for the first transistor, includes choosing a value for the adjustment material conductivity. 60. The method of claim 54, wherein choosing for the first transistor, includes choosing a value for the adjustment volume material. 61. A product made by the method of: providing an intermediate structure comprising: a body of material, the body having an adjustment layer comprising adjustment volume material, and an upper layer of semiconductor material, the upper layer overlying the adjustment layer,a gate conductor outside the body, the gate conductor having portions facing the body on at least three sides of the body and defining a channel volume of the body, the body having first and second longitudinally opposite end surfaces, the gate conductor extending beyond the body in both longitudinal directions, anda dielectric material between the gate conductor and the body;forming first and second additional semiconductor material on respectively the first and second end surfaces of the body; andforming source and drain volumes longitudinally adjacent to respectively the first and second additional semiconductor material,wherein the adjustment volume material has, at each longitudinal position, an electrical conductivity which differs from that of the upper layer of semiconductor material at the same longitudinal position, at least while the transistor is in an off-state,wherein the first additional material is less conductive than the source material, at least when the transistor is in the off state,and wherein the second additional material is less conductive than the drain material, at least when the transistor is in the off state. 62. An integrated circuit transistor structure comprising: a body of semiconductor material, the body having first and second longitudinally spaced doped source/drain volumes and further having at least first and second non-coplanar surfaces, the body further having a channel volume located longitudinally between the first and second source/drain volumes;a gate conductor disposed outside the body, the gate conductor having a first portion facing the first surface and a second portion facing the second surface and being located longitudinally at least partly along at least part of the channel volume; anda dielectric material between the first portion of the gate conductor and the first surface of the body and between the second portion of the gate conductor and the second surface of the body,the body containing an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced behind the second surface by a second distance and spaced longitudinally from both the first and second source/drain volumes,wherein the adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. 63. An integrated circuit transistor structure comprising: a body of semiconductor material, the body having first and second longitudinally spaced doped source/drain volumes and further having at least a first surface, the body further having a channel volume located longitudinally between the first and second source/drain volumes;a gate conductor disposed outside the body, the gate conductor having a first portion facing the first surface and being located longitudinally at least partly along at least part of the channel volume; anda dielectric material between the gate conductor and the first surface of the body,the body containing a dielectric material, spaced behind the first surface by a first distance and spaced longitudinally from both the first and second source/drain volumes, and disposed laterally within the channel volume so as to block off-state leakage current. 64. A method for fabricating an integrated circuit transistor structure comprising steps of: providing a body of semiconductor material, the body having first and second longitudinally spaced doped source/drain volumes and further having at least first and second non-coplanar surfaces, the body further having a channel volume located longitudinally between the first and second source/drain volumes;forming a gate conductor outside the body, the gate conductor having a first portion facing the first surface and a second portion facing the second surface and being located longitudinally at least partly along at least part of the channel volume;forming a dielectric material between the first portion of the gate conductor and the first surface of the body and between the second portion of the gate conductor and the second surface of the body; andforming an adjustment volume in the body, the adjustment volume being disposed longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced behind the second surface by a second distance and spaced longitudinally from both the first and second source/drain volumes,wherein the adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state.