초록 ▼

An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the

An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).

대표청구항 ▼

1. An integrated circuit structure comprising: a substrate;a metal gate located over the substrate;at least one liner layer over the substrate and substantially surrounding the metal gate;a spacer member adjacent the at least one liner layer;an at least partially oxidized etch stop layer located dir

1. An integrated circuit structure comprising: a substrate;a metal gate located over the substrate;at least one liner layer over the substrate and substantially surrounding the metal gate;a spacer member adjacent the at least one liner layer;an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including iridium (Ir) and having a thickness of approximately 0.5 nanometers; andwherein the at least partially oxidized etch stop layer is selectively formed over only the metal gate as a metal layer. 2. The integrated circuit structure of claim 1, wherein the etch stop layer is only partially oxidized, wherein only an outer portion of the etch stop layer is oxidized. 3. The integrated circuit structure of claim 1, wherein the etch stop layer is completely oxidized. 4. An integrated circuit structure comprising: a substrate;a metal gate located over the substrate;at least one liner layer over the substrate and substantially surrounding the metal gate;an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including iridium (Ir),wherein the at least partially oxidized etch stop layer is selectively formed over only the metal gate as a metal layer,wherein the at least partially oxidized etch stop layer has a thickness of approximately 0.5 nanometers (nm); anda dielectric layer over the at least partially oxidized etch stop layer. 5. The integrated circuit structure of claim 4, further comprising a contact extending through the dielectric layer and contacting the at least partially oxidized etch stop layer. 6. The integrated circuit structure of claim 5, further comprising a spacer member adjacent to the at least one liner layer, wherein the contact contacts the spacer member. 7. The integrated circuit structure of claim 4, wherein the etch stop layer is only partially oxidized, wherein only an outer portion of the etch stop layer is oxidized. 8. The integrated circuit structure of claim 4, wherein the etch stop layer is completely oxidized. 9. An integrated circuit structure comprising: a transistor structure having: a metal gate;a metal liner contacting the metal gate;a high-k liner surrounding the metal liner;spacers abutting the high-k liner; anda conductive layer below and alongside at least one of the spacers;an at least partially oxidized etch stop layer over only the metal gate, the metal liner and the high-k liner, exclusive of the spacers,wherein the at least partially oxidized etch stop layer has a thickness of approximately 0.5 nanometers (nm),wherein the at least partially oxidized etch stop layer includes iridium (Ir);a dielectric layer over the etch stop layer; anda contact contacting the conductive layer through the dielectric layer. 10. The integrated circuit structure of claim 9, wherein the contact further contacts at least one of the spacers and the at least partially oxidized etch stop layer. 11. The integrated circuit structure of claim 2, wherein the oxidized outer portion of the etch stop layer has a thickness of less than 0.5 nanometers. 12. The integrated circuit structure of claim 7, wherein the oxidized outer portion of the etch stop layer has a thickness of less than 0.5 nanometers. 13. The integrated circuit structure of claim 9, wherein the at least partially oxidized etch stop layer is only partially oxidized, wherein only an outer portion of the etch stop layer is oxidized, and wherein the oxidized outer portion of the etch stop layer has a thickness of less than 0.5 nanometers.