A system and method may monitor a mission critical processor power supply and recover from an intermittent power interruption. A subsystem of one or more processors may be tasked with a power monitoring function enabling processor self-monitoring and recovery. The subsystem monitors the power state
A system and method may monitor a mission critical processor power supply and recover from an intermittent power interruption. A subsystem of one or more processors may be tasked with a power monitoring function enabling processor self-monitoring and recovery. The subsystem monitors the power state of the processors and should a power interruption be sensed, the subsystem may be directed by a memory source external to the primary memory source for normal system operation. The subsystem directs each processing function within each processor to disable and remain disabled until the power interruption ceases. Once the power interruption is complete, the subsystem directs each processing function to refresh and restore to a previous state of full functionality.
대표청구항▼
1. A system for mission critical processor power event recovery, comprising: a mission critical processor configured for controlling a mission critical display, the mission critical processor including at least one core processor powered by a mission critical processor power supply;a first memory so
1. A system for mission critical processor power event recovery, comprising: a mission critical processor configured for controlling a mission critical display, the mission critical processor including at least one core processor powered by a mission critical processor power supply;a first memory source coupled with the mission critical processor and storing non-transitory processor readable program code to cause the mission critical processor to execute a normal operation of the mission critical display;a power warning monitor coupled with the mission critical processor and with the first memory source, and configured for receiving an indication of a power anomaly in the mission critical processor power supply;a capacitive power source coupled with the mission critical processor power supply, the capacitive power source configured for powering the mission critical processor and the power warning monitor during the power anomaly;at least one second memory source coupled with the power warning monitor and storing non-transitory processor readable program code to cause the power warning monitor to execute a power event operation and recovery of the mission critical processor during the power anomaly, the at least one second memory source separate from the first memory source;the power warning monitor further configured for: accessing the non-transitory processor readable program code from the first memory source and the at least one second memory source;receiving the indication of the power anomaly;notifying a user of the mission critical display of the power anomaly;saving to the at least one second memory source an execution context of at least one thread associated with the at least one core processor;redirecting the at least one thread to receive commands from the at least one second memory source;commanding the at least one thread to enter a power warning loop to preserve a status of the at least one thread;forcing the first memory source to execute a self-refresh;monitoring 1) the mission critical processor power supply for an end to the power anomaly and 2) a level of the capacitive power source;sensing an indication of the end to the power anomaly;when the monitoring reveals the end to the power anomaly: forcing the first memory source to cease the self-refresh;redirecting the at least one thread to receive commands from the first memory source;restoring the at least one thread with the saved execution context; andrestoring the mission critical display with information processed by the at least one thread. 2. The system for mission critical processor power event recovery of claim 1, wherein the mission critical processor is a multi-core processor including at least two core processors, each core processor of the at least two core processors further including at least one thread. 3. The system for mission critical processor power event recovery of claim 1, wherein receiving an indication of a power anomaly further comprises receiving an indication from a hardware based interrupt request (IRQ). 4. The system for mission critical processor power event recovery of claim 1, wherein the user is a flight crewmember and the mission critical display is a primary flight display for controlling an aircraft. 5. The system for mission critical processor power event recovery of claim 1, wherein the power anomaly is one of a voltage anomaly, a phase anomaly, and a frequency anomaly, and further including notifying the user of an exhaustion of the mission critical display before the level of the capacitive power source is zero. 6. The system for mission critical processor power event recovery of claim 1, wherein the execution context includes at least one parameter associated with a normal operation of the at least one thread. 7. The system for mission critical processor power event recovery of claim 1, wherein the first memory source is a memory controller supporting a self-refresh functionality and the at least one second memory source is at least one of: a core platform cache management static random access memory, a NOR flash read-only memory, a NAND flash memory, a magnetoresistive random-access memory, and a static RAM module. 8. The system for mission critical processor power event recovery of claim 1, wherein the power warning monitor is a field programmable gate array associated with the mission critical processor. 9. A method for mission critical processor power warning, comprising: monitoring a mission critical processor power supply for a power anomaly, the mission critical processor power supply coupled with a mission critical processor configured for controlling a mission critical display, the monitoring via a power warning monitor coupled with the mission critical processor;receiving an indication of the power anomaly;notifying a user of the mission critical display of the power anomaly;saving to at least one second memory source an execution context of at least one thread associated with at least one mission critical processor, the at least one second memory source configured for storing non-transitory processor readable program code to cause the power warning monitor to execute a power event operation and recovery of the mission critical processor during the power anomaly, the at least one second memory source separate from a first memory source, the first memory source configured for storing non-transitory processor readable program code for causing the mission critical processor to execute a normal operation of the at least one thread;redirecting the at least one thread to receive commands from the at least one second memory source;commanding the at least one thread to enter a power warning loop to preserve a status of the at least one thread;forcing the first memory source to execute a self-refresh;monitoring 1) the mission critical processor power supply for an end to the power anomaly and 2) a level of a capacitive power source, the capacitive power source powering the mission critical processor and the power warning monitor during the power anomaly;sensing an indication of the end to the power anomaly;when the monitoring reveals the end to the power anomaly: forcing the first memory source to cease the self-refresh;redirecting the at least one thread to receive commands from the first memory source;restoring the at least one thread with the saved execution context; andrestoring the mission critical display with information processed by the at least one thread. 10. The method for mission critical processor power warning of claim 9, wherein the mission critical processor is a multi-core processor including at least two core processors, each core processor of the at least two core processors further including at least one thread. 11. The method for mission critical processor power warning of claim 9, wherein receiving an indication of a power anomaly further comprises receiving an indication from a hardware based interrupt request (IRQ). 12. The method for mission critical processor power warning of claim 9, wherein the user is a flight crewmember and the mission critical display is a primary flight display for controlling an aircraft. 13. The method for mission critical processor power warning of claim 9, wherein the power anomaly is one of a voltage anomaly, a phase anomaly, and a frequency anomaly, and further including notifying the user of an exhaustion of the mission critical display before the level of the capacitive power source is zero. 14. The method for mission critical processor power warning of claim 9, wherein the execution context includes at least one parameter associated with a normal operation of the at least one thread. 15. The method for mission critical processor power warning of claim 9, wherein the first memory source is a memory controller supporting a self-refresh functionality and the at least one second memory source is at least one of: a core platform cache management static random access memory, a NOR flash read-only memory, a NAND flash memory, a magnetoresistive random-access memory, and a static RAM module. 16. A method for multiple core processor power event recovery, comprising: monitoring a mission critical processor power supply for a power anomaly, the mission critical processor power supply coupled with a mission critical multi-core processor, the mission critical multi-core processor configured for controlling a mission critical display;designating a primary thread associated with at least one core of the mission critical multi-core processor as a power warning monitor;the power warning monitor configured for executing non-transitory processor readable program code stored within at least one second memory source during the power anomaly, the non-transitory processor readable program code including the steps of: receiving an indication of the power anomaly;notifying a user of the mission critical display of the power anomaly;saving to the at least one second memory source an execution context of at least one local thread associated with the mission critical multi-core processor, the at least one second memory source configured for storing non-transitory processor readable program code to cause the power warning monitor to execute a power event operation and recovery of the mission critical multi-core processor during the power anomaly, the at least one second memory source separate from a first memory source, the first memory source configured for storing non-transitory processor readable program code to cause the mission critical processor to execute a normal operation of the at least one local thread;redirecting the at least one local thread to receive commands from the at least one second memory source;commanding the at least one local thread to enter a power warning loop to preserve a status of the at least one local thread;forcing the first memory source to execute a self-refresh;monitoring 1) the mission critical processor power supply for an end to the power anomaly and 2) a level of a capacitive power source, the capacitive power source configured for powering the power warning monitor during the power anomaly;sensing an indication of the end to the power event;forcing the first memory source to cease the self-refresh;redirecting the at least one local thread to receive commands from the first memory source;restoring the at least one local thread with the saved execution context; andrestoring the mission critical display with information processed by the at least one local thread. 17. The method for multiple core processor power event recovery of claim 16, wherein the user is a flight crewmember and the mission critical display is a primary flight display for controlling an aircraft. 18. The method for multiple core processor power event recovery of claim 16, wherein the power anomaly is one of a voltage anomaly, a phase anomaly, and a frequency anomaly, and further including notifying the user of an exhaustion of the mission critical display before the level of the capacitive power source is zero. 19. The method for multiple core processor power event recovery of claim 16, wherein the execution context includes at least one parameter associated with a normal operation of the at least one thread. 20. The method for multiple core processor power event recovery of claim 16, wherein the first memory source is a memory controller supporting a self-refresh functionality and the at least one second memory source is at least one of: a core platform cache management static random access memory, a NOR flash read-only memory, a NAND flash memory, a magnetoresistive random-access memory, and a static RAM module.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (13)
Jewett Douglas E. (Austin TX) Bereiter Tom (Austin TX) Vetter Brian (Austin TX), Fault-tolerant computer system with /CONFIG filesystem.
Jewett Douglas E. (Austin TX) Webster Phil (Austin TX) Aldridge Dave (Lago Vista TX) Norwood Peter C. (Austin TX) Mehta Nikhil A. (Austin TX), Fault-tolerant computer system with auto-restart after power-fall.
Jewett Douglas E. (Austin TX) Bereiter Tom (Austin TX) Vetter Brian (Austin TX) Banton Randall G. (Austin TX) Cutts ; Jr. Richard W. (Georgetown TX) Westbrook ; deceased Donald C. (late of Austin TX , Fault-tolerant computer system with online recovery and reintegration of redundant components.
Brant William A. ; Nielson Michael E. ; Tang Edde Tin-Shek, Power failure responsive apparatus and method having a shadow dram, a flash ROM, an auxiliary battery, and a controller.
Brooksby Glen William ; Harrison Daniel David ; Staver Daniel Arthur ; Berkcan Ertugrul ; Hoctor Ralph Thomas ; Daum Wolfgang ; Welles ; II Kenneth Brakeley, Reduced cost automatic meter reading system and method using locally communicating utility meters.
Govindaraj, Subbian; Urdaneta, Shelly Lynn; Cisler, Steven Mark; Weiland, Mark Joseph, Saving and restoring controller state and context in an open operating system.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.