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Providing a fine-grained arbitration system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/36
  • G06F-013/364
  • G06F-013/362
출원번호 US-0169515 (2014-01-31)
등록번호 US-9390039 (2016-07-12)
발명자 / 주소
  • Lai, Siaw Kang
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Trop, Pruner & Hu, P.C.
인용정보 피인용 횟수 : 0  인용 특허 : 39

초록

In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corre

대표청구항

1. An apparatus comprising: a first counter circuit including a plurality of first counters each associated with one of a plurality of requesters of a system on a chip (SoC) and to store a count of command units allocated to the corresponding requester, each of the command units corresponding to a c

이 특허에 인용된 특허 (39)

  1. Singla,Ankur; Nakil,Harshad; Reddy,Rajashekar, Advanced bandwidth allocation in PCI bus architecture.
  2. Mace, Timothy Charles; Tune, Andrew David, Apparatus and method for controlling issuing of transaction requests.
  3. Vishnu, Meenaradchagan, Arbiter for an input buffered communication switch.
  4. MacCormack, Andrew, Arbiter for arbitrating between a plurality of requesters and method thereof.
  5. Jurkevich Mark (Burtonsville MD) Bernstein Simon (Reston VA), Bandwidth seizing in integrated services networks.
  6. Paluzzi, Nicholas, Bus arbiter for a data storage system.
  7. Gulick Dale E., Bus arbiter including aging factor counters to dynamically vary arbitration priority.
  8. Hayashi,Atsushi; Shiraga,Mitsuaki; Yamanaka,Katsuhiko, Bus arbitration apparatus and bus arbitration method.
  9. Nunziata Ann B. (Cupertino CA) Moledina Riaz A. (Woodside CA) Ng Chi-Shing J. (San Jose CA), Bus arbitration scheme with priority switching and timer.
  10. O Mathuna, Padraig Gerard; Klaassen, Marc Gerardus, Bus bandwidth consumption profiler.
  11. Hirose,Yoshio; Utsumi,Hiroyuki; Saruwatari,Toshiaki, Bus control system for integrated circuit device with improved bus access efficiency.
  12. Boury Bechara F. (Boca Raton FL) Lohman Terence J. (Boca Raton FL) Nguyen Long D. (Boca Raton FL), CPU bus allocation control.
  13. Teh, Chee Hak; Hunter, Arthur, Demotion-based arbitration.
  14. Wille Ross M. (Sunnyvale CA) Carter Richard J. (Palo Alto CA), Distributed fair arbitration system using separate grant and request lines for providing access to data communication bu.
  15. Khurana,Sumit; Samtani,Sunil; Talpade,Rajesh, Dynamic bandwidth reallocation.
  16. Spencer David H. (Lebanon NJ) Becker Edward A. (Somerset NJ), Dynamic priority system for controlling the access of stations to a shared device.
  17. Lin,Chin Long; Wang,Ren Yuh, Memory bus assignment for functional devices in an audio/video signal processing system.
  18. Suzuki, Yoshito; Minami, Kouji, Memory control circuit and method for arbitrating memory bus.
  19. Cloonan, Thomas J.; Hickey, Daniel W., Method and apparatus for controlling traffic loading of different service levels in a cable data system.
  20. Kurts Tsvika,ILX, Method and apparatus for operating an adaptive multiplexed address and data bus within a computer system.
  21. Miller, Michael H.; Westby, Judy Lynn, Method and apparatus for preserving loop fairness with dynamic half-duplex.
  22. Weber, Wolf-Dietrich, Method and apparatus for scheduling a resource to meet quality-of-service restrictions.
  23. Randy B. Osborne ; David J. Harriman, Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect.
  24. Arimilli Ravi Kumar ; Dodson John Steven ; Lewis Jerry Don ; Williams Derek Edward, Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determin.
  25. Price, Roy F.; Paleja, Ameesh, Method and system for sharing segments of multimedia data.
  26. Gish,David W.; Massa,Don V., Method, system, and apparatus for an adaptive weighted arbiter.
  27. Weaver, Timothy H.; Whited, Albert, Methods, systems, and devices for bandwidth conservation.
  28. Lentz Derek J. (Los Gatos CA) Hagiwara Yasuaki (Santa Clara CA) Lau Te-Li (Palo Alto CA) Tang Cheng-Long (San Jose CA) Nguyen Le Trong (Monte Sereno CA), Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU.
  29. Beasley Michael W. (Owens Cross Roads AL), Minimum latency tie-breaking arbitration logic circuitry.
  30. Dale, Michele Z.; Latif, Farrukh A., Port manager controller for connecting various function modules.
  31. Gehman Judy M., Priority arbiter with shifting sequential priority scheme.
  32. Maergner, Juergen; Meritt, Allan S.; Nick, Jeffrey M; Wyman, Leslie W.; Yudenfriend, Harry M., Processing channel subsystem pending I/O work queues based on priorities.
  33. O\Connell Anne (Galway IEX) Creedon Tadhg (Galway IEX) Smith Deidre A. (Kildare IEX), Programmable priority arbiter.
  34. Lai, Siaw Kang, Providing a fine-grained arbitration system.
  35. Fukuyama,Toshihiro; Takai,Yuji; Kawamoto,Isao; Baba,Takahide; Murakami,Daisuke; Watanabe,Yoshiharu, Resource management device.
  36. Lee, Khee Wooi; Hunsaker, Mikal C.; Abramson, Darren L., Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools.
  37. Emnett Raymond F., System and method for arbitrating multi-function access to a system bus.
  38. Thorsbakken,Lloyd E.; Byers,Larry L., System and method for managing input/output requests using a fairness throttle.
  39. Asano,Shigehiro; Liu,Peichun Peter; Mui,David, Systems and methods for bandwidth shaping.
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