[특허]Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

Altera Corporation

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특허 상세정보

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내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/17 G06F-015/78 G06F-015/177
출원번호	US-0714993 (2015-05-18)
등록번호	US-9396161 (2016-07-19)
발명자 / 주소	Plunkett, Robert T. Heidari, Ghobad Master, Paul L.
출원인 / 주소	Altera Corporation
인용정보	피인용 횟수 : 0 인용 특허 : 430

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An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

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1. An adaptive computing integrated circuit configurable to perform a plurality of functions, comprising: a plurality of heterogeneous computational elements; andan interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network operative to configure the plurality of heterogeneous computational elements by changing interconnections between the plurality of heterogeneous computational elements;wherein a first group of heterogeneous computational elements is configurable by changing the interconnections of the interconnection network to form a first functional unit to implement a first function, the first function capable of being performed in parallel by multiple functional units;wherein a second group of heterogeneous computational elements is configurable by changing interconnections of the interconnection network to form a second functional unit to implement a second function; andwherein if the second function is not currently used, one or more of the second group of heterogeneous computational elements are reconfigurable by changing the interconnections of the interconnection network to implement the first function in parallel with the first group of heterogeneous computational elements. 2. The adaptive computing integrated circuit of claim 1, wherein the first functional unit forms a first version of a functional unit to implement the first function and wherein the one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form one or more additional instances of a second version of the functional unit to implement the first function. 3. The adaptive computing integrated circuit of claim 2, wherein one or more of the first group of heterogeneous computational elements or one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form a third version of a functional unit to implement the first function. 4. The adaptive integrated circuit of claim 2, wherein the second group of computational elements is reconfigured to the second version of the functional unit to perform the first function based on parameters including energy use, speed of performing the first function, or hardware availability. 5. The adaptive integrated circuit of claim 2, further comprising reallocating the first group of computational elements to perform a third function by changing the interconnections of the interconnection network after the second group of computational elements is reconfigured to the second version of the functional unit. 6. The adaptive computing integrated circuit of claim 1 wherein if the second function is not currently used, one or more of the first or second group of heterogeneous computational elements are reconfigurable by the interconnection network to implement a third function. 7. The adaptive computing integrated circuit of claim 1, wherein a third group of computational elements are configured to implement a third function, wherein the third group of computational elements are reconfigured as one of the multiple functional units to perform the first function if the third function is not used. 8. The adaptive integrated circuit of claim 1, wherein the first and second functions are part of a sequential operation and wherein the one or more of the second group of heterogeneous computational elements is reconfigured to perform the second function after the first function is performed. 9. An adaptive computing integrated circuit configurable to perform a plurality of functions, comprising: a plurality of heterogeneous computational elements; andan interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network operative to configure the plurality of heterogeneous computational elements by changing interconnections between the plurality of heterogeneous computational elements;wherein a first group of heterogeneous computational elements is configurable by changing the interconnections of the interconnection network to form a first functional unit to implement a first function;wherein a second group of heterogeneous computational elements is configurable by changing interconnections of the interconnection network to form a second functional unit to implement a second function; andwherein enhanced performance of the first function is executed by reconfiguring one or more of the second group of heterogeneous computational elements via changing the interconnections of the interconnection network to perform the first function. 10. The adaptive computing integrated circuit of claim 9, wherein the enhanced performance is executed by one or more of the second group of heterogeneous computational elements being reconfigured to form another functional unit to implement the first function. 11. The adaptive computing integrated circuit of claim 9, wherein one or more of the second group of computational elements are reconfigured to form a different version of a functional unit to perform the first function. 12. The adaptive computing integrated circuit of claim 9 wherein if the second function is not currently used, the one or more of the second group of heterogeneous computational elements are reconfigurable by the interconnection network to implement a third function. 13. The adaptive computing integrated circuit of claim 12, wherein a third group of the heterogeneous computational elements is allocated to implement the third function. 14. The adaptive computing integrated circuit of claim 9, wherein the enhanced version of the functional unit is formed based on a parameter including decreased energy use, increase speed of performing the function or hardware availability. 15. The adaptive integrated circuit of claim 9, wherein the first and second functions are part of a sequential operation and wherein the one or more of the second group of heterogeneous computational elements is reconfigured to perform the second function after the first function is performed according to the configuration information. 16. A method for allocating hardware computational elements within an adaptive computing integrated circuit, comprising: in response to first configuration information, allocating a first group of computational elements of the plurality of heterogeneous computational elements to form a first functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements, the first function capable of being performed in parallel by multiple function units;allocating a second group of computational elements of the plurality of heterogeneous computational elements to form a second functional unit to implement a second function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements; andreallocating at least some of the second group of heterogeneous computational elements allocated to the second functional unit to implement the first function in parallel with the first group of heterogeneous computational elements by changing the interconnections of the interconnection network. 17. The method of claim 16, wherein the second group of computational elements is reconfigured to the second version of the functional unit to perform the first function based on parameters including energy use, speed of performing the first function, or hardware availability. 18. The method of claim 16, wherein the first functional unit forms a first version of a functional unit to implement the first function and wherein the one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form one or more additional instances of a second version of the functional unit to implement the first function. 19. The method of claim 16, wherein one or more of the first group of heterogeneous computational elements or one or more of the second group of heterogeneous computational elements are reconfigurable via changing interconnections in the interconnection network to form a third version of a functional unit to implement the first function. 20. The method of claim 16, further comprising reallocating a third group of computational elements configured to implement a third function to be reconfigured as one of the multiple functional units to perform the first function if the third function is not used.

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Method and system for managing hardware resources to implement system functions using an adaptive computing architecture

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