Resistive random access memory with non-linear current-voltage relationship
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-045/00
G11C-013/00
출원번호
US-0733843
(2013-01-03)
등록번호
US-9406379
(2016-08-02)
발명자
/ 주소
Jo, Sung Hyun
Kim, Kuk-Hwan
출원인 / 주소
CROSSBAR, INC.
대리인 / 주소
Amin, Turocy & Watson, LLP
인용정보
피인용 횟수 :
0인용 특허 :
127
초록▼
Providing for fabrication, construction, and/or assembly of a resistive random access memory (RRAM) cell is described herein. The RRAM cell can exhibit a non-linear current-voltage relationship. When arranged in a memory array architecture, these cells can significantly mitigate sneak path issues as
Providing for fabrication, construction, and/or assembly of a resistive random access memory (RRAM) cell is described herein. The RRAM cell can exhibit a non-linear current-voltage relationship. When arranged in a memory array architecture, these cells can significantly mitigate sneak path issues associated with conventional RRAM arrays.
대표청구항▼
1. A resistive switching memory cell, comprising: a first metal layer comprising a first electrical conductive metal;a second metal layer comprising a second electrical conductive metal;a resistive switching material layer situated between the first metal layer and the second metal layer comprising
1. A resistive switching memory cell, comprising: a first metal layer comprising a first electrical conductive metal;a second metal layer comprising a second electrical conductive metal;a resistive switching material layer situated between the first metal layer and the second metal layer comprising a switching material that is an electrical insulator;a first semiconductor layer situated between the resistive switching material layer and the first metal layer comprising a lightly doped semiconductor material, wherein the first semiconductor layer is in contact with the resistive switching material layer and has a resistivity that measures between about 0.2 ohm-centimeter and about 20 ohm-centimeter; anda second semiconductor layer situated between the first semiconductor layer and the first metal layer comprising a highly doped semiconductor material, wherein the second semiconductor layer is between 5 nanometers and 100 nanometers thick and the highly doped semiconductor material comprises at least one of silicon, silicon germanium or a derivative of silicon germanium in a poly-crystalline phase. 2. The resistive switching memory cell of claim 1, wherein the second metal is an active metal that diffuses into the switching material in response to an electric field. 3. The resistive switching memory cell of claim 2, wherein the active metal comprises at least one of copper, titanium, or silver. 4. The resistive switching memory cell of claim 1, wherein the resistive switching material layer is between 2 nanometer and 100 nanometers thick and the switching material comprises at least one of silicon, silicon germanium, silicon dioxide, or a derivative of silicon dioxide. 5. The resistive switching memory cell of claim 1, wherein the first semiconductor layer is between 5 nanometers and 100 nanometers thick and the lightly doped semiconductor material comprises at least one of silicon, silicon germanium, or a derivative of silicon germanium in a poly-crystalline phase or an amorphous phase. 6. The resistive switching memory cell of claim 1, wherein a resistivity measurement of the second semiconductor layer is between 0.001 ohm-centimeter and 0.05 ohm-centimeter. 7. The resistive switching memory cell of claim 1, wherein the highly doped semiconductor material is a p (positive)-type semiconductor or an n (negative)-type semiconductor. 8. The resistive switching memory cell of claim 1, wherein the lightly doped semiconductor material is a p (positive)-type semiconductor or an n (negative)-type semiconductor. 9. The resistive switching memory cell of claim 1, wherein the first semiconductor layer comprises a depletion region in response to contact from a filament of the second electrical conductive metal that diffuses into the resistive switching material layer in response to an electric field, wherein a depth of the depletion region is a function of a voltage associated with the electric field. 10. A method for fabricating a resistive memory cell, comprising: including a heavily doped semiconductor stratum adjacent to a first electrode comprising a first electrical conductive stratum;including a lightly doped semiconductor stratum adjacent to the heavily doped semiconductor stratum;including a resistive switching material stratum comprising an electrical insulator material having a first resistance adjacent to the lightly doped semiconductor stratum and forming the resistive switching material stratum to be at least in part permeable to particles of a metal material; andincluding a second electrode comprising a second electrical conductive stratum comprising the metal material and adjacent to the resistive switching material stratum, wherein particles of the metal material, in response to a first bias, form a conductive path through the resistive switching material stratum having a second resistance lower than the first resistance, and wherein electrical continuity of the conductive path is broken in response to a second bias of different polarity from the first bias. 11. The method of claim 10, wherein the lightly doped semiconductor stratum is characterized by a resistivity of between 0.2 ohm-centimeter and 20 ohm-centimeter. 12. The method of claim 10, wherein the heavily doped semiconductor stratum is characterized by a resistivity of between 0.001 ohm-centimeter and 0.05 ohm-centimeter. 13. The method of claim 10, wherein the lightly doped semiconductor stratum comprises a p-type semiconductor material or an n-type semiconductor material. 14. The method of claim 10, wherein the heavily doped semiconductor stratum comprises a p-type semiconductor material or an n-type semiconductor material. 15. The method of claim 10, wherein including the resistive switching material stratum further comprising forming the resistive switching material stratum from an amorphous silicon material. 16. The method of claim 10, wherein including the lightly doped semiconductor stratum further comprising forming the lightly doped semiconductor stratum at a thickness within a range between about 5 nanometers(nm) and about 100 nm. 17. The method of claim 10, wherein including the resistive switching material stratum further comprising: forming the lightly doped semiconductor stratum comprising a p+ polycrystalline silicon or a p+ silicon germanium material; andforming the resistive switching material stratum from an upper region of the p+ polycrystalline silicon or the p+ silicon germanium material and into a non-conductive amorphous silicon having p-type impurities or a native silicon oxide. 18. A non-transitory computer-readable medium having instructions stored thereon that, in response to execution, cause a system including a processor to perform operations comprising: forming a heavily doped semiconductor stratum adjacent to a first electrode comprising a first electrical conductive stratum;forming a lightly doped semiconductor stratum adjacent to the heavily doped semiconductor stratum;forming a resistive switching material stratum comprising an electrical insulator material having a first resistance adjacent to the lightly doped semiconductor stratum and forming the resistive switching material stratum to be at least in part permeable to particles of a metal material; andforming a second electrode comprising a second electrical conductive stratum comprising the metal material and adjacent to the resistive switching material stratum, wherein particles of the metal material, in response to a first bias, form a conductive path through the resistive switching material stratum having a second resistance lower than the first resistance, and wherein electrical continuity of the conductive path is broken in response to a second bias of different polarity from the first bias. 19. The non-transitory computer-readable medium of claim 18, wherein the forming the resistive switching material stratum further comprising forming the resistive switching material stratum from an amorphous silicon material. 20. The non-transitory computer-readable medium of claim 18, wherein the forming the resistive switching material stratum further comprises: forming the lightly doped semiconductor stratum comprising a p+ polycrystalline silicon or a p+ silicon germanium material; andforming the resistive switching material stratum from an upper region of the p+ polycrystalline silicon or the p+ silicon germanium material and into a non-conductive amorphous silicon having p-type impurities or a native silicon oxide.
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