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An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon tran

An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.

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1. A method for operating a system, the system comprising: a data processor, the data processor having at least one arithmetic-logic unit and at least one cache;a bus system connecting the data processor to a receiver, the receiver comprising at least one of an external memory and an external periph

1. A method for operating a system, the system comprising: a data processor, the data processor having at least one arithmetic-logic unit and at least one cache;a bus system connecting the data processor to a receiver, the receiver comprising at least one of an external memory and an external peripheral; the bus system comprising a buffer memory; the buffer memory having three associated pointers: i. a first pointer to point to the buffer from which data is output from the buffer;ii. a second pointer to point the buffer location to which data is input to the buffer; andiii. a third pointer to store the value of the first pointer at the start of a data transfer;wherein the method of operations comprises: a. storing transfer data in the buffer memory;b. transmitting data to the receiver;c. the receiver transmitting information as to whether a data transfer was successful or has failed;d. if the transfer has failed, repeating the transfer of data from the buffer position indicated by the third associated pointer by resetting the first pointer with the value of the third. 2. The method according to claim 1, wherein step b comprises transmitting pluralities of data words combined into one data packet. 3. The method according to claim 1, wherein the bus system comprises a plurality of data buffers. 4. The method according to claim 1, wherein the bus system comprises a plurality of data channels. 5. The method according to claim 1, wherein the bus system is connected to a plurality of receivers and the method further comprises providing a module identifier (ID) to the at least the data processor and to each of the plurality of receivers. 6. The method according to claim 5, wherein the method further includes transmitting the module ID of a transmitter;transmitting the module ID of a target receiver; andtransmitting the address of a location within the target receiver. 7. The method of claim 6, further including multiplexors responsive to module IDs. 8. The method of claim 7, further including decoders connected to the multiplexors, the decoders operable to decode module IDs. 9. The method of claim 8 wherein a module ID is defined by a configuration unit. 10. A system comprising: on a chip: a plurality of processors;a cache system comprising a plurality of cache segments;an interconnect system; andat least one interface unit operable for transmitting data between the interconnect system and external devices via an external bus;wherein the interconnect system comprises: a plurality of data transmission segments arranged in a grid; wherein each data transmission segment comprises a logical connection to at least one other segment, whereby data is selectively transmitted to at least one other data transmission segment; and further whereinrespective of the plurality of the data transmission segments selectively interconnect each of the plurality of processors with at least one neighbor of said plurality of processors; andfurther respective of the plurality of the data transmission segments selectively interconnect each of the plurality of cache segments with at least one neighbor of said plurality of cache segments,the interconnection system further interconnecting each of the cache segments with each of the processors via the data transmission segments. 11. The system of claim 10, wherein the interconnect system comprises an arbiter, the arbiter controlling processor access to the interconnect system. 12. The system of claim 11 wherein the arbiter allows processor access in chronological sequence. 13. The system according to claim 10, wherein the at least one interface unit comprises a buffer memory; the buffer memory having three associated pointers: i. a first pointer to point to the buffer from which data is output from the buffer;ii. a second pointer to point the buffer location to which data is input to the buffer; andiii. a third pointer to store the value of the first pointer at the start of a data transfer;wherein the interface unit is to a. store transfer data in the buffer memory;b. transmit data to a selected one of said external devices;c. receive from the selected one of said external devices transmitting information as to whether a data transfer was successful or has failed;d. if the information indicates that data transfer has failed, repeat the data transfer from buffer position indicated by the third pointer. 14. The system according to claim 10 wherein said at least one interface unit is to store and transmit data to external devices in packets via a buffer memory. 15. The system according to claim 10, wherein each processor, cache segment, or interface unit further comprises a module identifier (ID). 16. The system according to claim 14 wherein said at least one interface unit is to store and transmit data to external devices in packets via said buffer memory; wherein each processor, cache segment, or interface unit further comprises a module identifier (ID); wherein the interface unit is to include a module ID in said data transfers, and further wherein the interface unit is further operable to generate time stamps that are transmitted with said data transfers. 17. The system according to claim 10 wherein the bus system is operable to transmit interrupt requests. 18. The system according to claim 10, further including a selector operable to select one of the cache segments based on an address associated with a data transfer. 19. The system of claim 10, wherein a cache segment is a separate memory; and further wherein each processor of the plurality of processors is connected to the cache system through the interconnect system. 20. The system of claim 10, wherein the cache segments are arranged in a column on the chip. 21. The system of claim 19, wherein the cache segments are arranged in a column on the chip.