최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0731316 (2015-06-04) |
등록번호 | US-9425272 (2016-08-23) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 15 인용 특허 : 549 |
A semiconductor chip region includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type (TT) and a GE of a first transistor of a second TT, a second CS that forms a GE of a second transistor of the first TT, a third CS that forms a GE
A semiconductor chip region includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type (TT) and a GE of a first transistor of a second TT, a second CS that forms a GE of a second transistor of the first TT, a third CS that forms a GE of a second transistor of the second TT, a fourth CS that forms a GE of a third transistor of the first TT, a fifth CS that forms a GE of a third transistor of the second TT, another CS that forms a GE of a fourth transistor of the first TT, and another CS that forms a GE of a fourth transistor of the second TT. The second and third transistors of the first and second TT's have a common diffusion terminal electrical connection and specified gate electrode electrical connections.
1. A semiconductor chip, comprising: a region including a plurality of transistors, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions, the region including at least eight conductive structures formed within the semic
1. A semiconductor chip, comprising: a region including a plurality of transistors, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions, the region including at least eight conductive structures formed within the semiconductor chip, some of the at least eight conductive structures forming at least one transistor gate electrode,each of the at least eight conductive structures respectively having a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,the top surfaces of the at least eight conductive structures co-planar with each other,each of the at least eight conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,each of the at least eight conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,wherein the first edge of each of the at least eight conductive structures is substantially straight,wherein the second edge of each of the at least eight conductive structures is substantially straight,each of the at least eight conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,each of the at least eight conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline,each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least eight conductive structures,wherein the at least eight conductive structures are positioned in a side-by-side manner such that each of the at least eight conductive structures is positioned to have at least a portion of its length beside at least a portion of the length of another of the at least eight conductive structures,wherein the width of each of the at least eight conductive structures is less than 45 nanometers, the region having a size of about 965 nanometers as measured in the second direction, each of the at least eight conductive structures positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least eight conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers,wherein the at least eight conductive structures includes a first conductive structure, the first conductive structure including a portion that forms a gate electrode of first transistor of a first transistor type, the first conductive structure including a portion that forms a gate electrode of a first transistor of a second transistor type,wherein the at least eight conductive structures includes a second conductive structure, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second conductive structure is of the first transistor type,wherein the at least eight conductive structures includes a third conductive structure, the third conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third conductive structure is of the second transistor type,wherein the at least eight conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth conductive structure is of the first transistor type,wherein the at least eight conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth conductive structure is of the second transistor type,wherein the first transistor of the first transistor type includes a first diffusion terminal and the second transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the first transistor type electrically connected to the first diffusion terminal of the second transistor of the first transistor type through a first electrical connection,wherein the first transistor of the second transistor type includes a first diffusion terminal, and the second transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the second transistor type electrically connected to the first diffusion terminal of the second transistor of the second transistor type through a second electrical connection,wherein the second transistor of the first transistor type includes a second diffusion terminal, and the third transistor of the first transistor type includes a first diffusion terminal, the second diffusion terminal of the second transistor of the first transistor type electrically connected to the first diffusion terminal of the third transistor of the first transistor type through a third electrical connection,wherein the second transistor of the second transistor type includes a second diffusion terminal, and the third transistor of the second transistor type includes a first diffusion terminal, the second diffusion terminal of the second transistor of the second transistor type electrically connected to the first diffusion terminal of the third transistor of the second transistor type through a fourth electrical connection,wherein the third transistor of the first transistor type includes a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the first transistor type through a fifth electrical connection,wherein the third transistor of the second transistor type includes a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the second transistor type through a sixth electrical connection,wherein the third electrical connection is electrically connected to the fourth electrical connection through a seventh electrical connection,wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the third transistor of the second transistor type through an eighth electrical connection,wherein the gate electrode of the third transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type through a ninth electrical connection,wherein each transistor of the first transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a second collection of transistors, wherein the first collection of transistors is separated from the second collection of transistors by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor. 2. The semiconductor chip as recited in claim 1, wherein the region includes a first interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level, the first interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,the first interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the first interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level,wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level, andwherein the fourth interconnect level is formed at a vertical position within the semiconductor chip above the third interconnect level. 3. The semiconductor chip as recited in claim 2, wherein the region includes a second interconnect conductive structure positioned next to and spaced apart from the first interconnect conductive structure in a same interconnect level as the first interconnect conductive structure, the second interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,the second interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the second interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure. 4. The semiconductor chip as recited in claim 3, wherein the first and second interconnect conductive structures are positioned such that a distance as measured in the second direction between their lengthwise centerlines is substantially equal to a second pitch, wherein the second pitch is a fractional multiple of the first pitch. 5. The semiconductor chip as recited in claim 4, wherein the second pitch is less than or equal to the first pitch. 6. The semiconductor chip as recited in claim 5, wherein at least one of the at least eight conductive structures within the region does not form a gate electrode of any transistor and has a width as measured in the second direction that is substantially equal to a width as measured in the second direction of another of the at least eight conductive structures. 7. The semiconductor chip as recited in claim 6, wherein the first and second interconnect conductive structures are positioned within either of the first interconnect level, the second interconnect level, or the third interconnect level. 8. The semiconductor chip as recited in claim 1, wherein the region includes a first interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level, the first interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,the first interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the first interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level,wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level, andwherein the fourth interconnect level is formed at a vertical position within the semiconductor chip above the third interconnect level. 9. The semiconductor chip as recited in claim 8, wherein the region includes a second interconnect conductive structure positioned in a same interconnect level as the first interconnect conductive structure, the second interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,the second interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the second interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure,wherein the first and second interconnect conductive structures are positioned next to and spaced apart from each other such that a distance as measured in the first direction between their lengthwise centerlines is substantially equal to a second pitch. 10. The semiconductor chip as recited in claim 9, wherein the region includes a third interconnect conductive structure positioned in the same interconnect level as the first and second interconnect conductive structures, the third interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the third interconnect conductive structure defined by a first end of the third interconnect conductive structure, a second end of the third interconnect conductive structure, a first edge of the third interconnect conductive structure, and a second edge of the third interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the third interconnect conductive structure is equal to a sum of a total distance along the first edge of the third interconnect conductive structure and a total distance along the second edge of the third interconnect conductive structure and a total distance along the first end of the third interconnect conductive structure and a total distance along the second end of the third interconnect conductive structure,wherein the total distance along the first edge of the third interconnect conductive structure is greater than two times the total distance along the first end of the third interconnect conductive structure,wherein the total distance along the first edge of the third interconnect conductive structure is greater than two times the total distance along the second end of the third interconnect conductive structure,wherein the total distance along the second edge of the third interconnect conductive structure is greater than two times the total distance along the first end of the third interconnect conductive structure,wherein the total distance along the second edge of the third interconnect conductive structure is greater than two times the total distance along the second end of the third interconnect conductive structure,wherein the first end of the third interconnect conductive structure extends from the first edge of the third interconnect conductive structure to the second edge of the third interconnect conductive structure and is located principally within a space between the first and second edges of the third interconnect conductive structure,wherein the second end of the third interconnect conductive structure extends from the first edge of the third interconnect conductive structure to the second edge of the third interconnect conductive structure and is located principally within the space between the first and second edges of the third interconnect conductive structure,the third interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the third interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the third interconnect conductive structure,wherein the second edge of the third interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the third interconnect conductive structure,wherein the third interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the third interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the third interconnect conductive structure,wherein the region includes a fourth interconnect conductive structure positioned in the same interconnect level as the first, second, and third interconnect conductive structures,the fourth interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the fourth interconnect conductive structure defined by a first end of the fourth interconnect conductive structure, a second end of the fourth interconnect conductive structure, a first edge of the fourth interconnect conductive structure, and a second edge of the fourth interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the fourth interconnect conductive structure is equal to a sum of a total distance along the first edge of the fourth interconnect conductive structure and a total distance along the second edge of the fourth interconnect conductive structure and a total distance along the first end of the fourth interconnect conductive structure and a total distance along the second end of the fourth interconnect conductive structure,wherein the total distance along the first edge of the fourth interconnect conductive structure is greater than two times the total distance along the first end of the fourth interconnect conductive structure,wherein the total distance along the first edge of the fourth interconnect conductive structure is greater than two times the total distance along the second end of the fourth interconnect conductive structure,wherein the total distance along the second edge of the fourth interconnect conductive structure is greater than two times the total distance along the first end of the fourth interconnect conductive structure,wherein the total distance along the second edge of the fourth interconnect conductive structure is greater than two times the total distance along the second end of the fourth interconnect conductive structure,wherein the first end of the fourth interconnect conductive structure extends from the first edge of the fourth interconnect conductive structure to the second edge of the fourth interconnect conductive structure and is located principally within a space between the first and second edges of the fourth interconnect conductive structure,wherein the second end of the fourth interconnect conductive structure extends from the first edge of the fourth interconnect conductive structure to the second edge of the fourth interconnect conductive structure and is located principally within the space between the first and second edges of the fourth interconnect conductive structure,the fourth interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the fourth interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the fourth interconnect conductive structure,wherein the second edge of the fourth interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the fourth interconnect conductive structure,wherein the fourth interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the fourth interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the fourth interconnect conductive structure,wherein the third and fourth interconnect conductive structures are positioned next to and spaced apart from each other such that a distance as measured in the first direction between their lengthwise centerlines is substantially equal to the second pitch. 11. The semiconductor chip as recited in claim 10, wherein at least one of the at least eight conductive structures within the region does not form a gate electrode of any transistor and has a width as measured in the second direction that is substantially equal to a width as measured in the second direction of another of the at least eight conductive structures. 12. The semiconductor chip as recited in claim 11, wherein the first, second, and third interconnect conductive structures are positioned within either of the first interconnect level, the second interconnect level, or the third interconnect level. 13. The semiconductor chip as recited in claim 1, wherein the eighth electrical connection includes one or more overlying interconnect conductive structures, or the ninth electrical connection includes one or more overlying interconnect conductive structures, or both the eighth and the ninth electrical connections include one or more overlying electrical connections, wherein each overlying interconnect conductive structure is formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the eighth or ninth electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the eighth or ninth electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline. 14. The semiconductor chip as recited in claim 1, wherein the lengthwise centerline of the second conductive structure is substantially aligned with the lengthwise centerline of the third conductive structure, and wherein the lengthwise centerline of the fourth conductive structure is substantially aligned with the lengthwise centerline of the fifth conductive structure. 15. The semiconductor chip as recited in claim 14, wherein a gate electrode of the fourth transistor of the first transistor type and a gate electrode of the fourth transistor of the second transistor type are formed by respective portions of a single one of the at least eight conductive structures. 16. The semiconductor chip as recited in claim 15, wherein at least one of the at least eight conductive structures within the region is a non-gate forming conductive structure that does not form a gate electrode of any transistor, the non-gate forming conductive structure positioned between at least two neighboring conductive structures of the at least eight conductive structures, with at least one of the at least two neighboring conductive structures forming at least one gate electrode of at least one transistor,the non-gate forming conductive structure positioned such that its lengthwise centerline is separated from the lengthwise centerlines of each of the at least two neighboring conductive structures by the first pitch as measured in the second direction,the non-gate forming conductive structure having a width as measured in the second direction that is substantially equal to a width as measured in the second direction of at least one of the at least two neighboring conductive structures. 17. The semiconductor chip as recited in claim 16, wherein the region includes a first connection forming conductive structure positioned to physically join to the top surface of the second conductive structure, wherein the first connection forming conductive structure is positioned a first connection distance away from a nearest gate electrode forming portion of the second conductive structure, the first connection distance measured in the first direction between closest located portions of the first connection forming conductive structure and the nearest gate electrode forming portion of the second conductive structure, wherein the region includes a second connection forming conductive structure positioned to physically join to the top surface of the third conductive structure, wherein the second connection forming conductive structure is positioned a second connection distance away from a nearest gate electrode forming portion of the third conductive structure, the second connection distance measured in the first direction between closest located portions of the second connection forming conductive structure and the nearest gate electrode forming portion of the third conductive structure,wherein the region includes a third connection forming conductive structure positioned to physically join to the top surface of the fourth conductive structure, wherein the third connection forming conductive structure is positioned a third connection distance away from a nearest gate electrode forming portion of the fourth conductive structure, the third connection distance measured in the first direction between closest located portions of the third connection forming conductive structure and the nearest gate electrode forming portion of the fourth conductive structure,wherein the region includes a fourth connection forming conductive structure positioned to physically join to the top surface of the fifth conductive structure, wherein the fourth connection forming conductive structure is positioned a fourth connection distance away from a nearest gate electrode forming portion of the fifth conductive structure, the fourth connection distance measured in the first direction between closest located portions of the fourth connection forming conductive structure and the nearest gate electrode forming portion of the fifth conductive structure,wherein at least two of the first, second, third, and fourth connection distances are different. 18. The semiconductor chip as recited in claim 17, wherein the seventh electrical connection includes one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline. 19. The semiconductor chip as recited in claim 18, wherein the eighth electrical connection includes one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline. 20. The semiconductor chip as recited in claim 14, wherein the eighth electrical connection includes one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the eighth electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline. 21. The semiconductor chip as recited in claim 14, wherein two of the first, second, third, fourth, and fifth conductive structures have different lengths. 22. The semiconductor chip as recited in claim 21, wherein the region includes a first connection forming conductive structure positioned to physically join to the top surface of the second conductive structure, wherein the region includes a second connection forming conductive structure positioned to physically join to the top surface of the third conductive structure,wherein the region includes a third connection forming conductive structure positioned to physically join to the top surface of the fourth conductive structure,wherein the region includes a fourth connection forming conductive structure positioned to physically join to the top surface of the fifth conductive structure,wherein at least one of the first, second, third, and fourth connection forming conductive structures is positioned at a respective location that is not directly above any gate electrode of any transistor of the first collection of transistors and that is not directly above any gate electrode of any transistor of the second collection of transistors and that is not directly above the inner sub-region of the region. 23. The semiconductor chip as recited in claim 22, wherein the first connection forming conductive structure is positioned a first connection distance away from a nearest gate electrode forming portion of the second conductive structure, the first connection distance measured in the first direction between closest located portions of the first connection forming conductive structure and the nearest gate electrode forming portion of the second conductive structure, wherein the second connection forming conductive structure is positioned a second connection distance away from a nearest gate electrode forming portion of the third conductive structure, the second connection distance measured in the first direction between closest located portions of the second connection forming conductive structure and the nearest gate electrode forming portion of the third conductive structure,wherein the third connection forming conductive structure is positioned a third connection distance away from a nearest gate electrode forming portion of the fourth conductive structure, the third connection distance measured in the first direction between closest located portions of the third connection forming conductive structure and the nearest gate electrode forming portion of the fourth conductive structure,wherein the fourth connection forming conductive structure is positioned a fourth connection distance away from a nearest gate electrode forming portion of the fifth conductive structure, the fourth connection distance measured in the first direction between closest located portions of the fourth connection forming conductive structure and the nearest gate electrode forming portion of the fifth conductive structure,wherein at least two of the first, second, third, and fourth connection distances are different. 24. The semiconductor chip as recited in claim 23, wherein the seventh electrical connection includes one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline. 25. The semiconductor chip as recited in claim 22, wherein at least two of the first, second, third, and fourth connection forming conductive structures is positioned at a respective location that is not directly above any gate electrode of any transistor of the first collection of transistors and that is not directly above any gate electrode of any transistor of the second collection of transistors and that is not directly above the inner sub-region of the region. 26. The semiconductor chip as recited in claim 25, wherein at least one of the at least eight conductive structures within the region is a non-gate forming conductive structure that does not form a gate electrode of any transistor, the non-gate forming conductive structure positioned between at least two neighboring conductive structures of the at least eight conductive structures, with at least one of the at least two neighboring conductive structures forming at least one gate electrode of at least one transistor,the non-gate forming conductive structure positioned such that its lengthwise centerline is separated from the lengthwise centerlines of each of the at least two neighboring conductive structures by the first pitch as measured in the second direction,the non-gate forming conductive structure having a width as measured in the second direction that is substantially equal to a width as measured in the second direction of at least one of the at least two neighboring conductive structures. 27. The semiconductor chip as recited in claim 26, wherein the region includes a first gate contact positioned to physically contact the top surface of the first conductive structure, the first gate contact substantially centered in the second direction upon the first conductive structure, the first gate contact formed to extend in a vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the first conductive structure through a dielectric material to contact at least one interconnect conductive structure, wherein the region includes a second gate contact positioned to physically contact the top surface of the second conductive structure, the second gate contact substantially centered in the second direction upon the second conductive structure, the second gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the second conductive structure through the dielectric material to contact at least one interconnect conductive structure,wherein the region includes a third gate contact positioned to physically contact the top surface of the third conductive structure, the third gate contact substantially centered in the second direction upon the third conductive structure, the third gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the third conductive structure through the dielectric material to contact at least one interconnect conductive structure,wherein the region includes a fourth gate contact positioned to physically contact the top surface of the fourth conductive structure, the fourth gate contact substantially centered in the second direction upon the fourth conductive structure, the fourth gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the fourth conductive structure through the dielectric material to contact at least one interconnect conductive structure,wherein the region includes a fifth gate contact positioned to physically contact the top surface of the fifth conductive structure, the fifth gate contact substantially centered in the second direction upon the fifth conductive structure, the fifth gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the fifth conductive structure through the dielectric material to contact at least one interconnect conductive structure. 28. The semiconductor chip as recited in claim 26, wherein the seventh electrical connection includes one or more overlying interconnect conductive structures formed at a respective vertical position within the semiconductor chip overlying some of the at least eight conductive structures so as to be separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material, wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective top surface with an entirety of a periphery of the respective top surface defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the respective top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end, wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end and is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge, wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first edge and the corresponding second edge,wherein each overlying interconnect conductive structure that is part of the seventh electrical connection has a respective lengthwise centerline oriented along its respective top surface to extend from its corresponding first end to its corresponding second end, with each of the corresponding first edge and the corresponding second edge being substantially straight and oriented substantially parallel to its respective lengthwise centerline. 29. A method for manufacturing an integrated circuit within a semiconductor chip, comprising: forming a plurality of transistors within a region of the semiconductor chip, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions, the plurality of transistors having respective gate electrodes formed by some of at least eight conductive structures present within the region,wherein forming the plurality of transistors includes forming each of the at least eight conductive structures to respectively have a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,the top surfaces of the at least eight conductive structures co-planar with each other,wherein forming the plurality of transistors includes forming each of the at least eight conductive structures to have a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,each of the at least eight conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,wherein the first edge of each of the at least eight conductive structures is substantially straight,wherein the second edge of each of the at least eight conductive structures is substantially straight,each of the at least eight conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,each of the at least eight conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline, wherein the width of each of the at least eight conductive structures is less than 45 nanometers,each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least eight conductive structures,wherein forming the plurality of transistors includes positioning the at least eight conductive structures in a side-by-side manner such that each of the at least eight conductive structures is positioned to have at least a portion of its length beside at least a portion of the length of another of the at least eight conductive structures,and wherein each of the at least eight conductive structures is positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least eight conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers,the at least eight conductive structures including a first conductive structure, the first conductive structure including a portion that forms a gate electrode of first transistor of a first transistor type, the first conductive structure including a portion that forms a gate electrode of a first transistor of a second transistor type,the at least eight conductive structures including a second conductive structure, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second conductive structure is of the first transistor type,the at least eight conductive structures including a third conductive structure, the third conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third conductive structure is of the second transistor type,the at least eight conductive structures including a fourth conductive structure, the fourth conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth conductive structure is of the first transistor type,the at least eight conductive structures including a fifth conductive structure, the fifth conductive structure including a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth conductive structure is of the second transistor type,the first transistor of the first transistor type including a first diffusion terminal electrically connected to a first diffusion terminal of the second transistor of the first transistor type through a first electrical connection,the first transistor of the second transistor type including a first diffusion terminal electrically connected to a first diffusion terminal of the second transistor of the second transistor type through a second electrical connection,the second transistor of the first transistor type including a second diffusion terminal electrically connected to a first diffusion terminal of the third transistor of the first transistor type through a third electrical connection,the second transistor of the second transistor type including a second diffusion terminal electrically connected to a first diffusion terminal of the third transistor of the second transistor type through a fourth electrical connection,the third transistor of the first transistor type including a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the first transistor type through a fifth electrical connection,the third transistor of the second transistor type including a second diffusion terminal electrically connected to a first diffusion terminal of a fourth transistor of the second transistor type through a sixth electrical connection,wherein the third electrical connection is electrically connected to the fourth electrical connection through a seventh electrical connection,wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the third transistor of the second transistor type through an eighth electrical connection,wherein the gate electrode of the third transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type through a ninth electrical connection,wherein each transistor of the first transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a second collection of transistors, wherein the first collection of transistors is separated from the second collection of transistors by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor,wherein the region has a size of about 965 nanometers as measured in the second direction. 30. The method as recited in claim 29, further comprising: forming a first interconnect conductive structure within the region at a position within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level,the first interconnect conductive structure formed to have a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,the first interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the first interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure,wherein the first interconnect level is located at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,wherein the second interconnect level is located at a vertical position within the semiconductor chip above the first interconnect level,wherein the third interconnect level is located at a vertical position within the semiconductor chip above the second interconnect level,wherein the fourth interconnect level is located at a vertical position within the semiconductor chip above the third interconnect level;forming a second interconnect conductive structure within the region at a position in a same interconnect level as the first interconnect conductive structure,the second interconnect conductive structure formed to have a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,the second interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the second interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure,wherein the first and second interconnect conductive structures are positioned next to and spaced apart from each other such that a distance as measured in the first direction between their lengthwise centerlines is substantially equal to a second pitch;forming a third interconnect conductive structure within the region at a position in the same interconnect level as the first and second interconnect conductive structures,the third interconnect conductive structure formed to have a top surface, an entirety of a periphery of the top surface of the third interconnect conductive structure defined by a first end of the third interconnect conductive structure, a second end of the third interconnect conductive structure, a first edge of the third interconnect conductive structure, and a second edge of the third interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the third interconnect conductive structure is equal to a sum of a total distance along the first edge of the third interconnect conductive structure and a total distance along the second edge of the third interconnect conductive structure and a total distance along the first end of the third interconnect conductive structure and a total distance along the second end of the third interconnect conductive structure,wherein the total distance along the first edge of the third interconnect conductive structure is greater than two times the total distance along the first end of the third interconnect conductive structure,wherein the total distance along the first edge of the third interconnect conductive structure is greater than two times the total distance along the second end of the third interconnect conductive structure,wherein the total distance along the second edge of the third interconnect conductive structure is greater than two times the total distance along the first end of the third interconnect conductive structure,wherein the total distance along the second edge of the third interconnect conductive structure is greater than two times the total distance along the second end of the third interconnect conductive structure,wherein the first end of the third interconnect conductive structure extends from the first edge of the third interconnect conductive structure to the second edge of the third interconnect conductive structure and is located principally within a space between the first and second edges of the third interconnect conductive structure,wherein the second end of the third interconnect conductive structure extends from the first edge of the third interconnect conductive structure to the second edge of the third interconnect conductive structure and is located principally within the space between the first and second edges of the third interconnect conductive structure,the third interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the third interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the third interconnect conductive structure,wherein the second edge of the third interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the third interconnect conductive structure,wherein the third interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the third interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the third interconnect conductive structure; andforming a fourth interconnect conductive structure within the region at a position in the same interconnect level as the first, second, and third interconnect conductive structures,the fourth interconnect conductive structure formed to have a top surface, an entirety of a periphery of the top surface of the fourth interconnect conductive structure defined by a first end of the fourth interconnect conductive structure, a second end of the fourth interconnect conductive structure, a first edge of the fourth interconnect conductive structure, and a second edge of the fourth interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the fourth interconnect conductive structure is equal to a sum of a total distance along the first edge of the fourth interconnect conductive structure and a total distance along the second edge of the fourth interconnect conductive structure and a total distance along the first end of the fourth interconnect conductive structure and a total distance along the second end of the fourth interconnect conductive structure,wherein the total distance along the first edge of the fourth interconnect conductive structure is greater than two times the total distance along the first end of the fourth interconnect conductive structure,wherein the total distance along the first edge of the fourth interconnect conductive structure is greater than two times the total distance along the second end of the fourth interconnect conductive structure,wherein the total distance along the second edge of the fourth interconnect conductive structure is greater than two times the total distance along the first end of the fourth interconnect conductive structure,wherein the total distance along the second edge of the fourth interconnect conductive structure is greater than two times the total distance along the second end of the fourth interconnect conductive structure,wherein the first end of the fourth interconnect conductive structure extends from the first edge of the fourth interconnect conductive structure to the second edge of the fourth interconnect conductive structure and is located principally within a space between the first and second edges of the fourth interconnect conductive structure,wherein the second end of the fourth interconnect conductive structure extends from the first edge of the fourth interconnect conductive structure to the second edge of the fourth interconnect conductive structure and is located principally within the space between the first and second edges of the fourth interconnect conductive structure,the fourth interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,wherein the first edge of the fourth interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the fourth interconnect conductive structure,wherein the second edge of the fourth interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the fourth interconnect conductive structure,wherein the fourth interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,wherein the fourth interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the fourth interconnect conductive structure,wherein the third and fourth interconnect conductive structures are positioned next to and spaced apart from each other such that a distance as measured in the first direction between their lengthwise centerlines is substantially equal to the second pitch.
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