Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/02
H01L-029/66
출원번호
US-0977135
(2015-12-21)
등록번호
US-9431243
(2016-08-30)
발명자
/ 주소
Lochtefeld, Anthony J.
Currie, Matthew T.
Cheng, Zhiyuan
Fiorenza, James
Braithwaite, Glyn
Langdo, Thomas A.
출원인 / 주소
Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
Slater Matsil, LLP
인용정보
피인용 횟수 :
1인용 특허 :
258
초록
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
대표청구항▼
1. A method comprising: forming a trench in a dielectric layer over top surface of a substrate, the substrate comprising a first crystalline semiconductor material, the trench being in the dielectric layer and having a length and a width adjoining the top surface of the substrate, the length being g
1. A method comprising: forming a trench in a dielectric layer over top surface of a substrate, the substrate comprising a first crystalline semiconductor material, the trench being in the dielectric layer and having a length and a width adjoining the top surface of the substrate, the length being greater than the width;forming a second crystalline semiconductor material in the trench and adjacent the first crystalline semiconductor material, the second crystalline semiconductor material being lattice mismatched to the first crystalline semiconductor material, dislocations in the second crystalline semiconductor material arising from the lattice mismatch terminating at a sidewall of the trench, a portion of the second crystalline semiconductor material extending out of the trench to form a fin;forming a gate structure over a top of the fin and along a sidewall of the fin; andforming a source/drain region defined in the fin proximate the gate structure. 2. The method of claim 1, wherein the dislocations propagate in a crystallographic direction parallel to the top surface of the substrate, the sidewall being oriented at an angle to the crystallographic direction, the angle being between 30° and 60°. 3. The method of claim 1, wherein the length is greater than a height of the sidewall. 4. The method of claim 1, wherein a ratio of a height of the sidewall to the width is greater than or equal to 2. 5. The method of claim 1, wherein the first crystalline semiconductor material is silicon. 6. The method of claim 1, wherein the second crystalline semiconductor material comprises germanium, a III-V semiconductor compound, or a combination thereof. 7. A method comprising: forming a dielectric layer over a top surface of a substrate, the substrate comprising a first crystalline semiconductor material;forming a trench being in the dielectric layer, the trench having a length and a width adjoining the top surface of the substrate, the length being greater than the width;forming a second crystalline semiconductor material in the trench and adjacent the first crystalline semiconductor material, the second crystalline semiconductor material being lattice mismatched to the first crystalline semiconductor material, dislocations in the second crystalline semiconductor material arising from the lattice mismatch terminating at a sidewall of the trench;forming a third crystalline semiconductor material disposed over the second crystalline semiconductor material, the third crystalline semiconductor material being a different material from the second crystalline semiconductor material; andforming a device formed at least partially in the third crystalline semiconductor material. 8. The method of claim 7, wherein the third crystalline semiconductor material is strained, the second crystalline semiconductor material inducing the strain in the third crystalline semiconductor material. 9. The method of claim 7, wherein a bandgap energy of the second crystalline semiconductor material is greater than a bandgap energy of the third crystalline semiconductor material. 10. The method of claim 7, wherein the forming a second crystalline semiconductor material in the trench and adjacent the first crystalline semiconductor material comprises epitaxially growing the second crystalline semiconductor material in the trench and adjacent the first crystalline semiconductor material. 11. The method of claim 7, wherein the device comprises a channel region and a source/drain region in the third crystalline semiconductor material. 12. The method of claim 7, wherein the dislocations propagate in a crystallographic direction parallel to the top surface of the substrate, the sidewall being oriented at an angle to the crystallographic direction, the angle being between 30° and 60°. 13. The method of claim 7, wherein the length is greater than a height of the sidewall. 14. The method of claim 7, wherein a ratio of a height of the sidewall to the width is greater than or equal to 2. 15. A method comprising: forming a dielectric layer having a trench over a top surface of a substrate, the substrate comprising a first crystalline semiconductor material, at least a portion of the first crystalline semiconductor material being in a top surface of the substrate and doped with dopants of a first dopant type, the trench being in the dielectric layer and having a length and a width adjoining the top surface of the substrate, the length being greater than the width; andforming a second crystalline semiconductor material having a first portion in the trench and adjacent the first crystalline semiconductor material and having a second portion over the first portion, the second crystalline semiconductor material being lattice mismatched to the first crystalline semiconductor material, dislocations in the first portion of the second crystalline semiconductor material arising from the lattice mismatch terminating at a sidewall of the trench, the first portion of the second crystalline semiconductor material being doped with dopants of the first dopant type, the second portion of the second crystalline semiconductor material being doped with dopants of a second dopant type, the second dopant type being opposite from the first dopant type. 16. The method of claim 15, wherein the first dopant type is a p-type dopant, and the second dopant type is an n-type dopant. 17. The method of claim 15, wherein the second crystalline semiconductor material has a third portion disposed between the first portion and the second portion, the third portion being intrinsic. 18. The method of claim 15, wherein the second portion extends above a top surface of the dielectric layer. 19. The method of claim 15, wherein the dislocations propagate in a crystallographic direction parallel to the top surface of the substrate, the sidewall being oriented at an angle to the crystallographic direction, the angle being between 30° and 60°. 20. The method of claim 15, wherein the length is greater than a height of the sidewall. 21. The method of claim 15, wherein a ratio of a height of the sidewall to the width is greater than or equal to 2.
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Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Method of making a monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substr.
Mosher Dan M. (Plano TX) Blanton Cornelia H. (Plano TX) Trogolo Joe R. (Plano TX) Latham Larry (Garland TX) Cotton David R. (Plano TX), Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices.
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Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate.
Calviello Joseph A. (Kings Park NY) Hickman Grayce A. (Hicksville NY), Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate.
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Gehrke, Thomas; Linthicum, Kevin J.; Davis, Robert F., Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates.
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Fan John C. C. (Chestnut Hill MA) Tsaur Bor-Yeu (Arlington MA) Gale Ronald P. (Bedford MA) Davis Frances M. (Framingham MA), Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth.
Simmons Jerry A. ; Sherwin Marc E. ; Drummond Timothy J. ; Weckwerth Mark V., Resonant tunneling device with two-dimensional quantum well emitter and base layers.
Salerno Jack P. (Waban MA) Lee Jhang W. (Mansfield MA) McCullough Richard E. (Wrentham MA), Selective OMCVD growth of compound semiconductor materials on silicon substrates.
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Ek Bruce A. (Pelham Manor NY) Iyer Subramanian S. (Yorktown Heights NY) Pitner Philip M. (Wappingers Falls NY) Powell Adrian R. (New Milford CT) Tejwani Manu J. (Yorktown Heights NY), Substrate for tensilely strained semiconductor.
Freundlich Alexandre (Houston TX) Vilela Mauro F. (Houston TX) Bensaoula Abdelhak (Houston TX) Ignatiev Alex (Houston TX), Tandem solar cell with improved tunnel junction.
Bedell,Stephen W.; Domenicucci,Anthony G.; Fogel,Keith E.; Leobandung,Effendi; Sadana,Devendra K., Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer.
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